PD - Principal, Physical Design (ASIC)

Location: Bay Area, United States; on-site

Company

hirify.global is an early-stage chiplet startup developing technologies for high-performance, manufacturable chiplet-based systems.

What you will do

• Drive ASIC physical design from RTL through GDSII, tapeout, and signoff.
• Lead architecture- and package-driven floorplanning, hierarchy integration, pin alignment, feedthrough planning, and routing resource reservation.
• Define clocking and CTS methodologies, including clock architectures, skew and latency targets, buffering, ICG strategy, shielding, and non-default routing rules.
• Establish DRC-aware power grid architectures and align power meshes across chip, subsystem, and block levels.
• Lead EM/IR analysis, identify hotspots, and optimize grid reinforcement and via structures while managing routing and congestion.
• Develop and improve physical design flows and methodologies for high-quality, on-time delivery.

Requirements

• 8–12 years of ASIC physical design experience, owning floorplanning, integration, clocking, and power planning through signoff and tapeout on complex SoCs.
• Expertise in hierarchy planning, lego-aligned boundaries, pin strategy, feedthrough and bus planning, and CTS methodologies such as spine-and-rib, H-tree, and mesh.
• Strong understanding of EM/IR, physical verification, static timing analysis, MMMC analysis, library corners, and skew-group balancing.
• Experience with advanced nodes such as TSMC 3nm, TSMC 2nm, or Samsung 2nm.
• Functional ECO execution experience.

Culture & Benefits

• Fast-paced early-stage startup environment.
• Cross-functional collaboration with experienced semiconductor industry experts.
• Focus on first-principles thinking, innovation, and high-volume manufacturable products.
• Excellent benefits and a collaborative work environment.