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Principal Physical Design Engineer (ASIC)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Principal Physical Design Engineer (ASIC): Developing cutting-edge chiplet-based ASICs from RTL to GDSII with an accent on floorplanning, clocking, power planning, and physical signoff. Focus on optimizing CTS, EM/IR performance, routing resources, MMMC timing behavior, and manufacturability for complex SoCs at advanced process nodes.

Location: Bay Area; on-site

Company

Early-stage chiplet startup developing ASIC technologies focused on power, area, manufacturability, and design flexibility.

What you will do

  • Drive ASIC development from RTL to GDSII across synthesis, place-and-route, static timing analysis, EM/IR analysis, and physical verification.
  • Develop architecture- and package-driven floorplans, physical partitions, hierarchy boundaries, pin alignment, feedthroughs, repeaters, buses, and routing corridors.
  • Define clocking and CTS methodologies, including clock architectures, skew and latency targets, buffering, ICG strategy, NDRs, shielding, skew groups, and balancing across MMMC variations.
  • Define power grid architectures with rings, straps, meshes, via patterns, and alignment across top-level, subsystem, and block-level designs.
  • Lead early and signoff EM/IR analysis, resolve hotspots, optimize vias, and align power planning with bump maps, current demand, package constraints, and analog routing requirements.
  • Improve design flows and methodologies to support high-quality, on-time delivery of high-volume, high-performance manufacturable products.

Requirements

  • 8–12 years of ASIC physical design experience, owning floorplanning, integration, clocking, and power planning from early feasibility through signoff and tapeout on complex SoCs.
  • Expertise in architecture- and package-driven hierarchy planning, lego-aligned boundaries, pin strategy, feedthrough, repeater and bus planning, and CTS methodologies using spine-and-rib, H-tree, or mesh architectures.
  • Strong awareness of EM/IR, physical verification, and static timing analysis, including MMMC, library corners, and skew-group balancing.
  • Experience with advanced process nodes, including TSMC 3nm, TSMC 2nm, or Samsung 2nm.
  • Functional ECO execution experience.

Culture & Benefits

  • Fast-paced early-stage startup environment.
  • Cross-functional collaboration with industry experts.
  • First-principles approach focused on innovation and high-performance manufacturable products.
  • Fun work environment with excellent benefits.

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