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12 часов назад

Senior Physical Design Engineer (ASIC)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Senior Physical Design Engineer (ASIC): Developing high-performance ASICs on advanced TSMC 5nm and 3nm process nodes with an accent on full-chip physical implementation, timing closure, power optimization, and signoff. Focus on implementing high-speed transceiver architectures, mitigating congestion and IR drop, and delivering tapeout-ready designs from RTL to GDSII.

Location: San Jose, United States

Company

hirify.global is a well-funded startup building photonics infrastructure for AI supercomputing, including optical interconnects and scalable photonic engines.

What you will do

  • Own block-level and full-chip physical implementation from RTL to GDSII for high-performance ASICs.
  • Perform floorplanning, placement, clock-tree synthesis, routing, physical verification, and signoff for advanced TSMC nodes.
  • Drive timing, power, and area closure in collaboration with RTL and STA teams.
  • Implement multi-voltage and multi-frequency designs, hierarchical flows, physical-aware synthesis, congestion mitigation, and skew optimization.
  • Perform tapeout signoff activities including PV, EM/IR, ESD, and eJobview.
  • Work with RTL, STA, IP, and verification teams to resolve implementation challenges in high-speed transceiver architectures.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
  • 8+ years of hands-on physical design experience, preferably with advanced technology nodes at 5nm or below.
  • Strong experience with floorplanning, placement, CTS, routing, IR drop mitigation, timing closure, and signoff debugging.
  • Hands-on experience with Synopsys ICC2, RedHawk SC, Cadence Innovus, Voltus, Siemens Calibre, or comparable industry tools.
  • Strong scripting skills in Tcl, Python, or Perl.

Nice to have

  • Physical design experience with high-speed PHYs such as SerDes or UCIe.
  • Experience with EM/IR analysis, power-grid optimization, congestion analysis, and advanced-node tapeout signoff.
  • Experience with high-frequency datapath or DSP-heavy designs.
  • Experience with TSMC CoWoS or SoIC-X 2.5D/3D designs.

Culture & Benefits

  • Comprehensive health insurance benefits.
  • Professional development opportunities and certification support.
  • Access to cutting-edge technology and cloud platforms.
  • Collaborative work with cross-functional engineering teams.
  • Competitive salary based on experience.

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