ASIC Physical Design Lead

Location: Remote across the United States

Company

hirify.global manages the application matching process on behalf of a partner company developing advanced semiconductor and SoC technologies.

What you will do

• Lead ASIC physical design from RTL handoff, floorplanning, and place-and-route through final GDSII delivery and tapeout.
• Define physical implementation strategies, methodologies, schedules, checkpoints, quality standards, budgets, and constraints for complex hierarchical SoC programs.
• Drive block-level and top-level implementation, clock-tree synthesis, timing closure, congestion mitigation, and PPA optimization across multiple modes, corners, and voltage domains.
• Own physical integrity and sign-off activities, including IR/EM analysis, thermal considerations, DRC, LVS, ERC, and other physical verification requirements.
• Collaborate with Architecture, RTL, Verification, DFT, Power, Packaging, and Signal Integrity teams on scan, BIST, bump planning, package-aware timing, and integration requirements.
• Mentor physical designers and improve automation scripts, methodologies, engineering practices, and design quality.

Requirements

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; an advanced degree is preferred.
• 8+ years of hands-on ASIC physical design experience with multiple successful tapeouts.
• Experience with advanced-node designs, preferably from 16nm to 3nm.
• Expertise in floorplanning, place-and-route, clock-tree synthesis, static timing analysis, timing closure, physical verification, sign-off, low-power design, and RTL-to-GDS flows.
• Strong proficiency with Cadence and/or Synopsys physical design toolchains, plus experience with UPF and/or CPF methodologies.
• Ability to provide technical leadership, mentor engineers, communicate technical decisions, and maintain ownership of schedules, quality, and delivery in a distributed engineering environment.

Culture & Benefits

• Remote work with a flexible location across the United States.
• Competitive salary and equity participation through Incentive Stock Options.
• Employer-paid medical insurance, HSA contributions, and dental and vision reimbursement.
• 401(k) retirement plan with employer matching.
• Flexible time off.
• Opportunity to shape physical design methodologies for advanced semiconductor and SoC products with demanding performance, power, and security requirements.

Hiring process

• hirify.global uses an AI-powered matching process to review applications against the role’s core requirements.
• Shortlisted candidates are shared with the hiring company, which manages interviews, assessments, and subsequent steps.