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11 часов назад

FPGA Post Silicon Validation Engineer (FPGA)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Malaysia
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
FPGA Post Silicon Validation Engineer (FPGA and SoC security): Validating FPGA configuration flows, secure boot, root-of-trust features, and HPS subsystems for next-generation FPGA and SoC devices with an accent on silicon bring-up, security, and system integrity. Focus on designing validation strategies, debugging boot and configuration failures, and building scalable automation for fault injection, negative testing, and cross-team platform validation.

Location: Penang 15, Penang, Malaysia

Company

hirify.global develops next-generation FPGA and SoC devices and related secure hardware platforms.

What you will do

  • Develop validation strategies for FPGA configuration, security, and HPS subsystems.
  • Validate power-on, cold, warm, partial, and recovery configuration flows.
  • Test secure boot, authentication, encryption, key management, root of trust, and protection against unauthorized access.
  • Validate HPS boot flows, reset and clock sequencing, memory interfaces, and FPGA-HPS integration.
  • Create test cases and vectors for corner cases, fault injection, negative testing, and configuration robustness.
  • Bring up devices and systems, debug failures across silicon revisions, and improve validation automation and infrastructure.

Requirements

  • Bachelor’s or Master’s degree in Electrical and Electronics Engineering, Computer Engineering, or a related field.
  • 8+ years of hands-on silicon validation experience focused on FPGA configuration, security, SoC, or embedded processor subsystems.
  • Strong understanding of FPGA configuration architectures, configuration memories, bitstream management, and recovery mechanisms.
  • Knowledge of hardware security concepts, including secure boot, authentication, encryption, key storage, lifecycle states, and threat modeling.
  • Experience validating HPS or embedded processor subsystems and performing system-level bring-up, debug, failure analysis, and silicon issue triage.
  • Experience with Python automation and test infrastructure; Verilog familiarity is an advantage.

Culture & Benefits

  • Regular full-time position.
  • Shift 1 aligned with Malaysia.
  • Collaboration with architecture, hardware, firmware, board design, and platform teams.
  • Hands-on exposure to secure FPGA architectures, SoC bring-up, embedded processors, and system-level debug.

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