PD - IP Lead – Sr Staff, Physical Design

Location: Bay Area, United States; Workplace: On-site

Company

hirify.global is an early-stage chiplet startup developing technologies for high-performance, power-efficient, manufacturable chiplet-based systems.

What you will do

• Define and execute IP block and partition physical design strategies aligned with tapeout schedules, resources, and milestones.
• Lead mixed-signal placement and routing, including analog keepouts, shielding, and DRC-aware methodologies.
• Own floorplanning, power planning, placement, clock-tree synthesis, routing, constraints, and hierarchical IP integration.
• Drive physical implementation from RTL handoff through GDSII, including ECOs, iteration management, and closure planning across corners.
• Develop and maintain custom flows for synthesis, PNR, EM/IR, STA, and physical verification, improving quality of results and predictability.
• Lead subsystem signoff and collaborate with frontend, DFT, packaging, and manufacturing teams to resolve integration and manufacturability risks.

Requirements

• Expertise in physical design, timing closure, and signoff for small to large ASIC IP blocks.
• Hands-on experience with floorplanning, power planning, placement, CTS, routing, EM/IR, STA, and physical verification across MMMC scenarios.
• Experience with mixed-signal integration and subsystem closure ownership.
• Ability to improve design flows through automation and scripting, with disciplined debugging and data-driven QoR and runtime optimization.
• Strong cross-functional leadership and communication skills for technical reviews and closure decisions under aggressive timelines.

Culture & Benefits

• Fast-paced early-stage startup environment focused on first-principles innovation.
• Collaboration with cross-functional semiconductor industry experts.
• Focus on high-volume, high-performance, and manufacturable products.
• Fun work environment with excellent benefits.