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4 дня назад

High Level Synthesis Compiler Engineer (FPGA)

124 100 - 179 700CAD
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
High Level Synthesis Compiler Engineer (FPGA) (C++/LLVM/MLIR): Developing and optimizing compiler infrastructure for FPGA design flows, including IR lowering, analysis and transformation passes, and correctness- and QoR-driven optimizations with an accent on scalable production systems. Focus on integrating compiler improvements with synthesis, timing, implementation, and debug flows, solving performance challenges on large designs, and translating customer requirements into practical engineering capabilities.

Location: Toronto, Ontario, Canada

Salary: $124.1K–$179.7K CAD annually, plus performance-based incentive opportunities.

Company

hirify.global develops FPGA design tools and compiler software for turning RTL and constraints into realizable designs.

What you will do

  • Develop and optimize compiler infrastructure for FPGA design flows, including IR lowering, analysis, transformation passes, and QoR-driven optimizations.
  • Improve compiler scalability, runtime, memory usage, correctness, and quality of results on large designs.
  • Work with customers to understand target applications, workflows, and success criteria, translating them into compiler and implementation-flow improvements.
  • Mentor engineers through code reviews, design reviews, pairing, and technical coaching.
  • Document compiler behavior, limitations, and workarounds for internal and external audiences.
  • Track developments in EDA, compiler, LLVM/MLIR, FPGA design, and relevant standards.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 8+ years of professional experience building compilers, LLVM/MLIR-based tools, or EDA/FPGA implementation software.
  • Strong C++ experience with production systems, performance optimization, multithreading, and large codebases.
  • Hands-on experience with LLVM and/or MLIR, including IR design, compiler passes, backends, or integration into a larger compiler or EDA flow.
  • Strong digital design and FPGA knowledge, including LUT, FF, BRAM, DSP, clocks, timing, and QoR implications.
  • Experience with FPGA or ASIC implementation flows, including synthesis, place-and-route, STA, and constraints, plus strong customer communication and mentoring skills.

Nice to have

  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Exposure to simulation, formal verification, debug environments, or high-level design flows such as HLS.
  • Experience shipping software used by external customers or large internal user bases.

Culture & Benefits

  • Regular full-time employment on Shift 1 in Canada.
  • Performance-based incentive opportunities tied to individual contributions and company success.
  • Canadian work experience is not required.
  • Artificial intelligence is used to screen, assess, or select applicants.

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