Staff Design Verification Engineer (SystemVerilog/UVM)

Location: Austin, Texas, United States. Must provide proof of the right to work in the United States of America. The role involves access to export-controlled technology and may require export authorization or an export license.

Compensation may include base pay, variable or incentive compensation, equity, healthcare, retirement plans, and paid time off.

Company

hirify.global develops high-performance RISC-V compute platforms for data-intensive applications across markets including AI, machine learning, automotive, data center, mobile, and consumer technology.

What you will do

• Own verification planning and execution for high-performance out-of-order CPU core areas, including Frontend, Midcore, Load-Store Unit, and Hardware Prefetch.
• Drive block-level and core-level debug, coverage analysis, and coverage closure for complex CPU features and microarchitectural behavior.
• Define verification strategies for instruction fetch, branch prediction, issue and dispatch, pipeline interactions, load/store ordering, hazards, memory consistency, and prefetch correctness.
• Develop verification environments, checkers, scoreboards, assertions, stimulus, and coverage models using scalable methodology.
• Partner with architecture, RTL, performance, compiler, system verification, and software teams to identify gaps and clarify specifications.
• Lead root-cause analysis and contribute reusable infrastructure, methodology, and technical guidance across future CPU core generations.

Requirements

• 7+ years of relevant experience in ASIC, CPU/core, SoC, or IP/component functional verification.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Direct CPU/core verification experience and deep knowledge of computer architecture and CPU microarchitecture.
• Experience with verification planning, constrained-random or directed stimulus, failure analysis, coverage analysis, and coverage closure.
• Authorization to work in the United States is required, along with successful background and reference checks and export-control eligibility.

Nice to have

• Experience with out-of-order core verification, formal verification, or emulation.
• Experience with high-performance CPU areas such as memory ordering, consistency, execution units, or RVV Vector Units.
• Experience mentoring engineers and influencing verification methodology beyond an immediate block or feature.
• Familiarity with Python, C/C++, or other programming languages used for verification infrastructure and automation.

Culture & Benefits

• Collaborative work across architecture, design, performance, and verification teams.
• Comprehensive benefits may include healthcare, retirement plans, paid time off, variable or incentive compensation, and equity.
• Inclusive equal-opportunity workplace committed to diversity.

Hiring process

• Employment is contingent on successful background and reference checks.
• New hires must complete Form I-9 employment eligibility verification.