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Staff Design Verification Engineer – High Performance CPU Core (RISC-V)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Staff Design Verification Engineer – High Performance CPU Core (RISC-V): Driving verification planning, execution, debug, and coverage closure for high-performance out-of-order CPU core areas with an accent on SystemVerilog/UVM environments, microarchitectural correctness, and scalable verification methodology. Focus on identifying verification gaps, solving complex pipeline, memory-ordering, branch-prediction, and hardware-prefetch challenges, and achieving signoff-quality coverage.

Location: Austin, Texas, United States. Right to work in the United States is required; the position is subject to export-control authorization requirements.

Company

hirify.global develops high-performance RISC-V compute platforms and CPU cores for data-intensive applications across artificial intelligence, machine learning, automotive, data center, mobile, and consumer markets.

What you will do

  • Own verification planning and execution for one or more high-performance out-of-order CPU core areas, including Frontend, Midcore, Load-Store Unit, Hardware Prefetch, and related core-level interactions.
  • Drive block-level and core-level planning, debug, coverage analysis, and coverage closure for complex CPU features and microarchitectural behavior.
  • Define verification strategies for instruction fetch, branch prediction, issue and dispatch, pipeline interactions, load/store ordering, hazards, memory consistency, and hardware prefetch correctness.
  • Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases.
  • Partner with architecture, RTL, performance, and verification teams to review specifications, identify ambiguity, improve debugability, and achieve signoff quality.
  • Drive root-cause analysis across specifications, RTL, test content, and verification infrastructure, while contributing reusable methodology and technical guidance.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • At least 7 years of relevant experience in ASIC, CPU/core, or SoC design verification. The posting also references 5–8 years of relevant IP/component functional-verification experience, preferably in core/CPU verification.
  • Strong hands-on experience with SystemVerilog and UVM-based verification.
  • Direct CPU/core verification experience and a strong understanding of computer architecture and CPU microarchitecture.
  • Experience in at least one high-performance CPU area, such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
  • Strong knowledge of verification-flow methodology, including test planning, constrained-random or directed stimulus, failure analysis, coverage analysis, and coverage closure.
  • Strong debugging skills and the ability to translate architectural intent into verification strategy and execution.
  • Experience developing with object-oriented programming principles.

Nice to have

  • Experience with out-of-order core verification.
  • Experience using formal verification and/or emulation for high-risk or performance-sensitive verification problems.
  • Experience collaborating with performance, compiler, system-verification, and software teams to close verification gaps.
  • Experience mentoring engineers and influencing verification methodology beyond an immediate block or feature area.
  • Familiarity with Python, C/C++, or other scripting and programming languages used for design-verification infrastructure and automation.

Culture & Benefits

  • Collaborative work with architecture, RTL, performance, verification, and software teams on high-performance RISC-V CPU cores.
  • Comprehensive benefits may include healthcare, retirement plans, and paid time off.
  • The role may be eligible for variable or incentive compensation and/or equity.
  • Employment is contingent on successful background and reference checks, proof of US work authorization, and export-control authorization.
  • hirify.global is an equal-opportunity employer committed to an inclusive environment.

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