13 часов назад
Digital Verification Engineer (ASIC)
131 000 - 243 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Digital Verification Engineer (ASIC): Building and verifying digital modules for Neuralink's brain-computer interface SoCs with an accent on high-throughput, low-power digital signal processing and complex ASIC verification. Focus on developing SystemVerilog testbenches, automation flows, coverage and regressions, and validating power-aware designs through formal, gate-level, FPGA, and emulation workflows.
Location: South San Francisco, California, United States
Base salary: $131,000–$243,000 USD per year, plus equity compensation in the form of RSUs for full-time employees.
Company
develops brain-computer interface devices designed to restore movement and sight and transform interaction with digital systems.
What you will do
- Verify digital modules and complex system-on-chip designs for implantable brain-computer interfaces.
- Develop SystemVerilog testbenches, functional models, and verification environments.
- Build automation flows and scripts using Python, Perl, Makefile, Tcl, and UNIX shell.
- Set up regressions, code coverage, testing, debugging, and diagnostic workflows.
- Support verification across architecture, microarchitecture, RTL, physical design, FPGA, emulation, and lab bring-up.
- Validate high-throughput, low-power digital signal-processing systems and power-aware designs.
Requirements
- At least 3 years of experience in digital ASIC verification.
- Excellent SystemVerilog skills.
- Experience with automation flows and scripting using Python, Perl, Makefile, Tcl, and UNIX shell.
- Experience with code coverage and regression setup.
- Experience building testbenches, testing, and debugging complex SoC systems.
- Knowledge of verification methodologies such as UVM, processor architectures including ARM or RISC-V, and AMBA bus.
Nice to have
- Experience with formal verification, SystemC/C++ functional modeling, and logic verification.
- Experience with IEEE-1801 (UPF) simulation flows, low-power gate-level simulation, and low-power formal verification.
- Experience with FPGA or emulation, lab system bring-up, diagnostics, and lab debugging.
Culture & Benefits
- Opportunity to work on brain-computer interface technology with multidisciplinary experts.
- Growth opportunities and rapid advancement for high-impact contributors.
- Medical, dental, and vision insurance through a PPO plan.
- Paid holidays, flexible time off, commuter benefits, and provided meals.
- Equity through RSUs, a 401(k) plan, and parental leave for eligible full-time employees.
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