Staff ASIC Design Engineer (AI)

Location: US Headquarters

Base salary: $195,000–$226,000 per year, depending on location, experience, and comparable employee compensation. New-hire and annual RSU grants are also offered.

Company

hirify.global develops edge AI-based computer vision SoCs for autonomous driving, ADAS, intelligent video security, robotics, and other embedded applications.

What you will do

• Design and implement video compression, image processing, vector computation, flexible compute systems, processor cores, and memory subsystems for edge AI and LLM inference.
• Develop, implement, and verify RTL using Verilog and SystemVerilog.
• Synthesize and optimize RTL for timing, area, and power.
• Evaluate micro-architecture and architectural tradeoffs through rapid modeling with Python, Perl, and other scripting languages.
• Develop front-end design methodologies and tool flows, and participate in chip bring-up and testing.
• Review code and functional coverage and recommend actions to close verification gaps.

Requirements

• Master’s degree in Electrical, Electronics, or Computer Engineering.
• 5–10 years of experience in VLSI or ASIC design.
• Strong understanding of computer architecture, logic design, and VLSI design.
• Knowledge of SystemVerilog, Verilog, Python, Perl, design verification, and functional coverage.
• Ability to write scripting and assembly language programs.
• Strong communication, problem-solving, and teamwork skills.

Nice to have

• Knowledge of logic synthesis and timing closure.

Culture & Benefits

• Opportunity to work across video compression, image processing, vector computation, processor cores, memory subsystems, and flexible compute architectures.
• Broad ownership from micro-architecture and RTL design through silicon bring-up.
• Work on products for real-world edge AI, automation, robotics, and intelligent low-power embedded systems.
• Competitive benefits and RSU grant opportunities.