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2 дня назад

Senior Hardware Design Engineer (AI)

120 000 - 200 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Senior Hardware Design Engineer (AI): Designing and implementing SystemVerilog RTL blocks for Reconfigurable Dataflow Unit ASICs powering AI workload acceleration systems with an accent on computer architecture, high-speed digital design, and PPA optimization. Focus on carrying hardware blocks from microarchitecture and verification through tapeout, silicon bring-up, and post-silicon debugging.

Location: Onsite in San Jose, California, or Austin, Texas, United States

Salary: $120,000–$200,000 USD annually

Company

hirify.global develops a full-stack generative AI platform, including the SN40L chip and integrated on-premises and cloud solutions for enterprise and government organizations.

What you will do

  • Author microarchitecture specifications for compute, memory, or networking subsystems with principal engineers and architects.
  • Code, integrate, and debug SystemVerilog RTL for assigned ASIC blocks throughout implementation and production.
  • Optimize blocks against Power, Performance, and Area targets using advanced digital design techniques.
  • Collaborate with verification and physical design engineers on functionality, timing, and area convergence.
  • Implement SystemVerilog Assertions and run lint, CDC, and LEC flows.
  • Participate in design reviews and support tapeout, silicon bring-up, and post-silicon debugging.

Requirements

  • Master's degree in Computer Engineering or Electrical Engineering with 3–5 years of relevant experience, or bachelor's degree with 5–7 years.
  • Strong foundation in computer architecture, digital logic design, and SystemVerilog RTL design for high-performance ASICs.
  • Experience making Power, Performance, and Area trade-offs and using synthesis tools and Static Timing Analysis.
  • Knowledge of interconnects and protocols such as AXI, PCIe, Ethernet, HBM, or DDR.
  • Experience with linting, Clock Domain Crossing, Logical Equivalence Checking, SystemVerilog Assertions, and hardware performance analysis.
  • Python and Linux shell scripting skills, Git familiarity, and ability to work onsite in San Jose or Austin.

Nice to have

  • Experience with the full ASIC development cycle through tapeout and production silicon.
  • Knowledge of AI workload acceleration techniques and low-power design methods such as clock gating or DVFS.
  • Exposure to emulation or FPGA prototyping for pre-silicon validation.

Culture & Benefits

  • Full-time US employment includes base salary, equity, and benefits.
  • Medical insurance is covered at 95% for employees and 77% for dependents, with an employer-contributed HSA.
  • Dental, vision, disability, life, AD&D, and flexible spending account options are available.
  • Well-being benefits include Headspace, Gympass+, One Medical, and counseling through an Employee Assistance Program.

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