Director of ASIC Design Verification (AI)

Location: San Jose, California, United States

Salary: $270,000–$340,000 USD base salary per year

Company

hirify.global develops a full-stack generative AI platform, including the SN40L chip, software, models, and cloud or on-premises deployment.

What you will do

• Own pre-silicon functional and performance verification for complex machine learning ASICs through coverage closure, tape-out, and readiness sign-off.
• Define verification architecture, strategy, schedules, environments, test benches, agents, checkers, and stimulus across block, full-chip, system, and gate levels.
• Act as the technical authority for verification methodology, coverage criteria, testbench architecture, regression health, and complex failure debug.
• Support first-silicon lab validation and bring-up, tracing functional issues to root cause and feeding findings back into pre-silicon verification.
• Lead and grow a team of 8–10 verification engineers, including principal-level engineers, while owning staffing, leveling, hiring, coaching, and technical development.
• Partner with architecture, design, software, compiler, runtime, hardware, systems, physical design, process, quality, and product teams.

Requirements

• 12+ years of industry experience in ASIC design verification, or equivalent experience, with a BS in EE, CS, or CE.
• 5+ years managing design verification engineers, including hiring and performance management for senior and principal-level engineers.
• Full-cycle design verification experience from planning through tape-out and production silicon on at least one complex ASIC or large subsystem.
• Deep hands-on expertise in SystemVerilog, SVA, Python, and verification methodologies such as UVM, OVM, or VMM.
• Experience with silicon bring-up, lab functional validation, and debugging first-silicon issues to root cause.
• Working knowledge of machine learning SoCs or CPU/GPU architectures and excellent stakeholder communication skills.

Nice to have

• MS or PhD in EECS with 15+ years of ASIC design verification experience.
• Experience leading multiple large-scale chips to silicon and scaling DV teams through increased headcount or chip complexity.
• Expertise in performance verification, PCIe, Ethernet, memory subsystems, advanced TSMC nodes, multi-die or chiplet verification, emulation, or FPGA prototyping.
• Experience managing cross-site or distributed teams and applying Claude or other AI tools to verification workflows.

Culture & Benefits

• Full-time US employment with equity and benefits.
• Medical insurance with 95% employee premium coverage and 77% dependent premium coverage, plus an employer-contributed HSA.
• Dental, vision, disability, life, AD&D, and flexible spending account options.
• Well-being benefits including Headspace, Gympass+, One Medical, and employee assistance counseling.