Principal RTL Design Engineer (AI Hardware)

Location: San Jose, California, United States

Base salary: $180,000–$255,000 USD per year

Company

Develops a full-stack generative AI platform powered by the SN40L reconfigurable dataflow processor for enterprise and government workloads.

What you will do

• Own microarchitecture and synthesizable SystemVerilog RTL implementation for major RDU blocks or subsystems from specification through tape-out.
• Design compute datapaths, on-chip networks, or memory subsystems and optimize pipelining, retiming, frequency, power, performance, and area.
• Drive timing closure with synthesis, static timing analysis, critical-path iteration, floorplan feedback, and congestion analysis.
• Own lint, CDC, LEC, and SystemVerilog Assertions quality gates, while partnering with verification on coverage and functional and gate-level debug.
• Prototype and evaluate AI acceleration features with architecture, software, and compiler teams.
• Set design standards through technical reviews, methodology improvements, AI and EDA automation, and mentoring.

Requirements

• BS or MS in electrical engineering, computer engineering, or computer science, with 7+ years of ASIC RTL design experience or equivalent industry experience.
• Mastery of synthesizable SystemVerilog and SVA for high-speed, high-performance ASICs.
• Experience with datapath pipelining, retiming, critical-path restructuring, and aggressive frequency targets.
• Strong knowledge of computer architecture and digital logic, including arbitration, flow control, clock-domain crossing, and memory structures.
• Ownership of a complex ASIC block or subsystem from microarchitecture specification through tape-out on at least one production ASIC.
• Experience with physical-design constraints, PPA trade-offs, synthesis, STA, lint, CDC, LEC, and Python-based design automation.

Nice to have

• Expertise in compute and dataflow datapaths, on-chip networks, interconnects, or memory subsystems.
• Experience with AXI, PCIe, Ethernet, HBM, or DDR.
• Knowledge of AI/ML acceleration, dataflow or reconfigurable architectures, formal property checking, TSMC nodes, chiplets, or multi-die design.
• Performance modeling, architectural trade-off analysis, or use of AI tools such as Claude in RTL design and flow development.
• MS or PhD with 10+ years of ASIC RTL design experience.

Culture & Benefits

• Full-time US employment includes base salary, equity, and benefits.
• Medical insurance covers 95% of employee premiums and 77% of dependent premiums, with an employer-funded HSA contribution.
• Dental, vision, disability, life, AD&D, and flexible spending account options are available.
• Well-being benefits include Headspace, Gympass+, One Medical, counseling, and an Employee Assistance Program.