Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Очень мало
90к-166к CAD/год
230к CAD260к CADмедиана270к CAD
По похожим ролям (50) ~ 260к CAD/год
На СНГ рынке: $3к/мес ($3к - $3к)
88
Крутая вакансия
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Высококачественная вакансия от мирового лидера в области EDA с четко определенным кругом задач и отличным соцпакетом, что гарантирует стабильность и престиж.
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Современный стекЧеткие задачиТоповый работодательОтличные бенефитыВилка зарплаты
Оценка от Hirify AI
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Lead Digital Verification Engineer (SystemVerilog): Developing and verifying high-performance digital RTL and reusable verification components for industry-standard physical IP protocols with an accent on verification architecture, UVM, assertions, and coverage closure. Focus on building verification environments, planning and executing tests, closing functional and code coverage, and collaborating across digital, analog, physical design, and project teams.
Location: Full-time onsite work in the Montreal, Quebec, Canada office; the role is also listed for Montreal, Ottawa, and Toronto, with up to 5% travel as required.
Salary: CAD 89,600–166,400 annually, plus potential incentive compensation, bonus, equity, and benefits.
Company
hirify.global develops high-performance physical IP and electronic design technologies for industry-standard protocols.
What you will do
Verify digital RTL modules and develop reusable verification components and environments.
Contribute to verification flow development, verification plan creation and execution, stimulus generation, and coverage analysis.
Identify, plan, and implement functional coverage, checks, and SystemVerilog assertions.
Drive functional and code coverage closure across the end-to-end digital verification flow.
Collaborate with digital and analog design, physical design, production, verification, and project management teams across worldwide locations.
Work independently within project timelines while communicating project development progress and status.
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, applied sciences, or a related field.
Understanding of verification architecture, verification methodologies, Metric Driven Verification, and Universal Verification Methodologies.
Understanding of functional coverage and checks, SystemVerilog Assertions, and the digital design flow.
Fundamental knowledge of digital design and verification principles.
Strong problem-solving and communication skills, with the ability to work independently and collaborate in a focused engineering team.
Ability to communicate in English.
Nice to have
Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, applied sciences, or a related field.
Experience coding with SystemVerilog UVM.
Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk.
Exposure to standard protocols including PCIe, USB, SATA, Ethernet, DisplayPort, or HDMI.
Exposure to formal verification technologies, mixed-signal design, hirify.global tools, and low-power verification using CPF or UPF.
Culture & Benefits
Paid vacation, holidays, and leave-of-absence programs.
RRSP, TFSA, Employee Stock Purchase Plan, and a funded Lifestyle Spending Account.
Group health coverage including dental, vision, and Emotional Wellbeing Support benefits for eligible dependents.
Life insurance, short-term and long-term disability coverage, Global Travel Medical coverage, and Business Travel Accident Insurance.
Equal-opportunity workplace committed to a diverse workforce and accessibility during the application and interview process.
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