Member of Technical Staff - Formal Verification Engineer (AI/ASIC)

Location: On-site in Palo Alto, California, United States

Company

hirify.global is a frontier AI lab developing specialized computing systems and custom hardware for next-generation AI workloads.

What you will do

• Own formal verification of AI-generated chip design artifacts from early specifications through tape-out.
• Develop formal verification plans, identify critical properties, and define verification closure criteria for hardware blocks and subsystems.
• Build Spec to SVA flows, formal testbenches, and environments covering functional requirements, interface protocols, and corner cases.
• Drive proofs using abstraction, decomposition, invariants, and solver strategies; diagnose inconclusive results and improve proof convergence.
• Debug counterexamples with RTL designers and convert discovered bugs into regression properties.
• Automate formal regressions, result tracking, failure triage, and reusable verification components.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Strong SystemVerilog and SVA skills, with the ability to read complex RTL and understand microarchitecture.
• Hands-on experience with formal tools such as Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal.
• Understanding of model checking, induction, abstraction, and assume-guarantee reasoning.
• Experience reasoning about control logic, pipelines, arbitration, buffering, interface protocols, reset behavior, backpressure, and concurrent transactions.
• Strong scripting skills in Python, Tcl, or similar languages, plus the ability to resolve ambiguity and make technical decisions under tape-out deadlines.

Nice to have

• Formal verification sign-off experience for blocks or subsystems in a shipped chip.
• Experience with AI accelerators, processor cores, cache coherence, memory systems, or interconnects.
• Simulation-based verification and UVM experience.
• Experience building formal verification infrastructure across multiple projects or teams.
• Familiarity with AI-generated RTL or early technical roles at semiconductor or EDA startups.

Culture & Benefits

• Competitive salary and meaningful equity stake.
• Fast-paced startup environment with autonomy and visible impact.
• Foundational work at the intersection of formal verification, AI, and silicon.