RTL Verification Engineer (AI)

Location: Remote, associated with Palo Alto and U.S. locations

Salary: $160,000–$240,000 per year, plus equity, benefits, and 401(k).

Company

hirify.global is a startup building foundational technology to improve performance, scalability, and resiliency in large-scale AI data center clusters.

What you will do

• Develop and maintain RTL verification environments using UVM or equivalent methodologies.
• Create coverage-driven verification plans and develop directed and constrained-random tests for ASIC and FPGA designs.
• Analyze simulation results, debug verification and design issues, and perform root-cause analysis with RTL design engineers.
• Implement functional and code coverage, develop reusable verification components, and write SystemVerilog Assertions.
• Automate regression testing and improve verification infrastructure using Python and scripting.
• Participate in design and verification reviews, contributing to testability, correctness, optimization, and verification closure.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in digital design verification.
• Strong hands-on experience with SystemVerilog, UVM or similar methodologies, Python, and industry-standard EDA tools such as VCS, Questa, or Xcelium.
• Experience verifying AXI, AXI-S, APB, PCIe, Ethernet, SPI, and I²C protocols.
• Experience with formal verification, processor subsystems, or SoC-level designs.
• Strong analytical, communication, organizational, and independent execution skills.

Culture & Benefits

• Remote work within a company operating across U.S. and Canadian locations.
• Collaboration with experienced builders and operators who have founded and scaled companies.
• Culture centered on trust, integrity, respect, shared responsibility, and accountability.
• Meaningful equity, benefits, and 401(k).