Principal Verification Engineer (SystemVerilog)

Location: Austin (Oakhill, Office), United States; onsite position.

Company

Develops digital IP, sensor, and processing technologies for automotive and advanced microcontroller businesses, supporting secure connected vehicles and autonomous vehicles.

What you will do

• Drive a zero-defect mindset across the verification team and provide technical leadership on complex verification challenges.
• Define and execute verification plans, including directed and constrained-random stimulus.
• Develop verification testbenches and components such as drivers, monitors, scoreboards, and advanced UVM VIPs.
• Analyze RTL, functional coverage, assertion coverage, simulation results, and automated test environments.
• Define functional coverage models, develop and maintain SystemVerilog assertions, and apply formal verification methodologies.
• Debug failures through reproduction and root-cause analysis while mentoring and growing a small engineering team.

Requirements

• BSEE with 5+ years of semiconductor industry experience, or MSEE with 3+ years of experience, or PhD with 1+ years of experience.
• Knowledge of DDR, PCIe, or AMBA protocols, including CHI, ACE, and AXI.
• Strong expertise in Verilog and SystemVerilog.
• Experience with OVM/UVM and class-based verification methodologies.
• Experience with formal verification methodologies.
• Experience using AI/LLM-based approaches to improve engineering efficiency.
• Experience with test pattern debugging and validation in simulation and automated test environments.
• Scripting experience with Python, Perl, and UNIX/Linux.
• Familiarity with functional and code coverage methodologies, plus strong analytical, problem-solving, and debugging skills.

Nice to have

• VHDL experience.
• Familiarity with major simulation and debug tools.

Culture & Benefits

• Full-time employment in an office-based Austin location.
• Equal opportunity and affirmative action employment practices.
• Reasonable accommodations are available for otherwise qualified disabled individuals.