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8 часов назад

VLSI Design Verification Engineer_2

Формат работы
onsite
Тип работы
fulltime
Английский
b2
Страна
Taiwan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
VLSI Design Verification Engineer_2 (SystemVerilog/UVM): Developing and executing verification plans, testbenches, assertions, and coverage models for complex SoCs and IPs with an accent on coverage-driven and assertion-based verification. Focus on debugging next-generation designs, collaborating with architects and post-silicon teams, and applying AI-assisted tools to accelerate verification workflows.

Location: Hsinchu, Taiwan

Company

hirify.global develops AI vision processors for edge applications that extract data from high-resolution video streams.

What you will do

  • Develop and execute verification plans for complex SoCs and IPs.
  • Build testbenches, assertions, and coverage models using advanced verification methodologies.
  • Apply SystemVerilog/UVM, coverage-driven, and assertion-based verification techniques.
  • Collaborate with architects, designers, and post-silicon teams.
  • Ensure the correctness and reliability of next-generation silicon designs.

Requirements

  • Bachelor’s, Master’s, or PhD in electrical engineering, computer science, or a related field.
  • Strong background in digital design and computer architecture.
  • Experience with SystemVerilog, UVM, Verilog, C, and C++.
  • Strong debugging, analytical, and problem-solving skills.

Nice to have

  • Experience scripting with Perl or Python.

Culture & Benefits

  • Work on cutting-edge verification flows supported by AI-powered tools.
  • Collaborate with global engineers on next-generation SoCs.
  • Work in a learning-driven environment focused on professional growth.

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