Senior RTL Design Engineer (RISC-V Cache Subsystem)

Location: Hsinchu, Taiwan. Right to work in Taiwan is required. Access to export-controlled technology is subject to applicable authorization or export approvals.

Company

hirify.global develops high-performance compute platforms and CPU core solutions based on the open-source RISC-V architecture for applications including AI, machine learning, automotive, data centers, mobile, and consumer devices.

What you will do

• Architect, design, and implement high-performance cache subsystems for RISC-V CPU core generators.
• Enhance features and performance in existing cache subsystem designs.
• Develop microarchitecture specifications and maintain design documentation.
• Perform initial sandbox verification and collaborate with verification engineers on detailed test plans.
• Work with physical implementation engineers to meet frequency, area, and power targets.
• Collaborate with performance modeling engineers on performance exploration and optimization.

Requirements

• At least three years of relevant industry experience designing high-performance, energy-efficient cache subsystems, ideally for CPU or GPU subsystems.
• Successful cache subsystem development experience from architecture through tapeout.
• Expertise in multilevel coherent cache architectures and designs.
• Experience with TileLink or a similar interconnect architecture.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Bachelor’s or Master’s degree in electrical engineering, computer engineering, computer science, or a related discipline, or equivalent experience.

Nice to have

• Knowledge of RISC-V architecture.
• Experience with Scala or Chisel.
• Understanding of UVM, Formal, and other IP verification tools and methodologies.
• Knowledge of an object-oriented or functional programming language.

Culture & Benefits

• Collaborative engineering culture focused on knowledge sharing and high-quality design.
• Opportunity to work on innovative processor and hardware IP projects.
• Inclusive workplace and equal employment opportunity commitment.
• Employment is contingent on successful background and reference checks.