Staff Design Verification Engineer (Cache Verification)

Location: Hsinchu, Taiwan. Right to work in Taiwan is required.

Company

hirify.global develops high-performance RISC-V compute platforms for applications including artificial intelligence, machine learning, automotive, data center, mobile, and consumer electronics.

What you will do

• Own verification planning and execution for L2/L3 caches and related cache-subsystem features from block-level verification through subsystem integration.
• Build and maintain SystemVerilog and UVM verification environments, including checkers, scoreboards, assertions, stimulus, and coverage models.
• Develop directed and constrained-random tests for cache coherency, ordering, flow control, concurrency, backpressure, and error scenarios.
• Analyze failures, isolate root causes, and drive fixes across specifications, RTL, testbench infrastructure, assertions, and test content.
• Collaborate with architecture, design, and verification teams to clarify requirements and improve verification quality.
• Analyze coverage, close coverage holes, and contribute reusable methodology, automation, and debug improvements.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of ASIC, CPU, or SoC design verification experience with ownership of complex block- or subsystem-level verification.
• Strong expertise in SystemVerilog and UVM-based verification.
• Strong understanding of cache architecture, memory hierarchy, cache coherency, computer architecture, and microarchitecture.
• Experience building reusable testbenches, assertions, checkers, scoreboards, coverage models, and debug infrastructure.
• Experience with coverage analysis and closure, constrained-random verification, metrics-driven signoff, and root-cause debugging.

Nice to have

• Experience verifying multiple cache levels, including private and shared cache structures.
• Experience with memory consistency, weak ordering, multicore verification, performance-oriented verification, formal techniques, or emulation/FPGA-assisted debug.
• Familiarity with Python, C/C++, or scripting languages for design verification infrastructure and automation.
• Ability to influence technical direction across architecture, design, and verification teams.

Culture & Benefits

• Full-time individual-contributor position at Staff Engineer level.
• Cross-functional collaboration with architecture, design, and verification teams.
• Employment is contingent on successful background and reference checks.
• Access to export-controlled technology requires authorization under applicable export control laws or approved export licenses.
• Inclusive, equal-opportunity workplace committed to diversity.