Staff RTL Design Engineer (RISC-V)

Location: Hsinchu, Taiwan

Company

hirify.global develops high-performance compute platforms and CPU cores based on the open-source RISC-V architecture for applications including AI, machine learning, automotive, data centers, mobile, and consumer technology.

What you will do

• Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.
• Develop and specify CPU microarchitecture, documenting decisions and sharing technical knowledge.
• Perform initial sandbox verification and collaborate with the design verification team on comprehensive test plans.
• Work with the physical implementation team to optimize designs for frequency, area, and power targets.
• Collaborate with performance modelling engineers on performance exploration and optimization.

Requirements

• More than 5 years of experience in RTL design for CPU products.
• BS or MS degree in electrical engineering, computer engineering, computer science, or a related technical field, or equivalent experience.
• Academic or professional experience with CPU RTL design.
• Proficiency in Verilog, SystemVerilog, or VHDL for hardware RTL design.
• Knowledge of at least one object-oriented or functional programming language.
• Must provide proof of the right to work in Taiwan. Employment is also subject to authorization to access export-controlled technology and applicable export licenses or approvals.

Nice to have

• Knowledge of the RISC-V architecture.
• Experience with Scala and/or Chisel.
• Strong attention to detail and focus on high-quality design.

Culture & Benefits

• Collaborative engineering culture focused on knowledge sharing and teamwork.
• Fast-paced environment focused on bringing new hardware IP to market quickly with high quality and performance.
• Inclusive workplace committed to diversity and equal opportunity.
• Background and reference checks are required.