RTL Design Engineer (RISC-V)

Location: Hsinchu, Taiwan. Right to work in Taiwan is required. Employment is subject to export-control authorization for access to controlled technology.

Company

hirify.global develops high-performance compute platforms and CPU cores based on the open-source RISC-V architecture for applications including AI, automotive, data centers, mobile, and consumer devices.

What you will do

• Architect, design, and implement features, performance improvements, and ISA extensions in RISC-V CPU core generators.
• Develop and specify CPU microarchitecture and document design decisions.
• Perform initial sandbox verification and create thorough verification plans with the design verification team.
• Collaborate with the physical implementation team to optimize frequency, area, and power.
• Work with the performance modelling team on performance exploration and optimization.

Requirements

• BS/MS degree in electrical engineering, computer engineering, computer science, or a related discipline, or equivalent experience.
• Academic or professional experience with CPU RTL design.
• Proficiency in Verilog, SystemVerilog, or VHDL.
• Knowledge of at least one object-oriented or functional programming language.
• Strong attention to detail and commitment to high-quality design.
• Ability to collaborate effectively in a team-oriented engineering environment.

Nice to have

• Knowledge of the RISC-V architecture.
• Experience with Scala or Chisel.

Culture & Benefits

• Collaborative design culture with knowledge sharing and documentation.
• Inclusive environment committed to diversity and equal opportunity.
• Successful background and reference checks are required.