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Principal Digital Verification Engineer (SystemVerilog/UVM)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US/Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal Digital Verification Engineer (SystemVerilog/UVM): Developing state-of-the-art testbenches, unit- and chip-level test cases, and verification methodologies for connectivity PHYs, controllers, and chiplet-based systems with an accent on coverage-driven verification, simulation environments, and regression automation. Focus on leading end-to-end product verification, building constrained-random and gate-level verification flows, integrating third-party VIPs, and guiding junior engineers.

Location: On-site in Vancouver, BC or the Bay Area, CA

Company

Early-stage chiplet startup developing high-performance, manufacturable technologies for chiplet-based systems, including PHYs and controllers.

What you will do

  • Provide technical verification leadership for connectivity IPs, chiplets, PHYs, controllers, and company products, including guidance for junior verification engineers.
  • Develop and execute verification plans, test plans, coverage reviews, and progress tracking through RTL freeze.
  • Create and maintain SystemVerilog/UVM-based block- and chip-level testbenches, test cases, assertions, DPI-based firmware simulation environments, and gate-level simulation environments.
  • Drive constrained-random, coverage-driven, silicon, functional, and power verification methodologies.
  • Maintain automated regression environments and verification flows supporting design CI/CD pipelines.
  • Collaborate with design engineers, integrate third-party VIPs and mixed-signal IPs, ensure protocol compliance, and coordinate feature and bug tracking.

Requirements

  • BS in Electrical Engineering or a related field and 15+ years of experience.
  • Strong expertise in UVM, SystemVerilog test-environment development, and assertion coding.
  • Strong expertise in coverage-driven verification.
  • Proficiency with third-party tools for regression management and coverage analysis.
  • Experience with connectivity interfaces and protocols.
  • Experience verifying third-party mixed-signal IPs and integrating VIPs.
  • Strong debugging skills and a strong bias toward innovation, automation, and verification quality improvement.
  • Strong understanding of microcontroller architecture and peripherals communicating with microcontrollers.
  • Hands-on experience with at least one scripting language.
  • Proven experience working in a startup-like environment.

Nice to have

  • Knowledge of I/O interfaces.

Culture & Benefits

  • Fast-paced early-stage startup environment focused on innovation and first-principles engineering.
  • Cross-functional collaboration with engineering experts.
  • Work on high-volume, high-performance, and manufacturable chiplet products.
  • Fun work environment with excellent benefits.

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