DV - Digital Verification Engineer (Senior Levels - Staff +)
Контакты
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US/Canada
ci cdethernetstartupsystemveriloguvmdpihbmassertion codingdigital verificationchipletsverification automation
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TL;DR
DV - Digital Verification Engineer (SystemVerilog/UVM, Ethernet/Chiplets): Developing state-of-the-art testbenches, unit- and chip-level test cases, and verification environments for connectivity IPs, chiplets, PHYs, and controllers with an accent on serial transmission protocols, Ethernet standards, and coverage-driven verification. Focus on building regression and CI/CD environments, verifying high-speed 100G–800G Ethernet features, integrating third-party VIPs and mixed-signal IPs, and maintaining DPI-based firmware and GLS simulation environments.
Location: On-site in Vancouver, BC, Canada or the Bay Area, California, United States.
Company
Early-stage chiplet startup developing high-volume, high-performance chiplet-based systems with a focus on power, area, manufacturability, and design flexibility.
What you will do
Develop and execute verification plans for connectivity IPs and chiplets, including block- and chip-level test cases.
Create and maintain SystemVerilog/UVM verification environments, assertions, testbenches, and regression infrastructure.
Enable design CI/CD pipelines and track verification progress toward RTL freeze through test-plan and coverage reviews.
Collaborate with design engineers on microarchitecture, test planning, coverage, design quality, and Ethernet standards compliance.
Integrate third-party VIPs, verify mixed-signal IPs, and coordinate feature and bug-tracking requests.
Develop and maintain DPI-based firmware simulation and GLS environments for functional and power simulations, while providing technical leadership to junior verification engineers.
Requirements
Master’s or Ph.D. in Electrical Engineering or a related field with 6+ years of experience.
Hands-on experience verifying serial transmission protocols and products, preferably retimers, gearboxes, or Ethernet PMA/PCS logic.
Strong expertise in UVM, SystemVerilog test-environment development, and assertion coding.
Proficiency with third-party tools for regression management and coverage analysis.
3+ years of experience working with Ethernet IEEE 802.3 standards clauses related to 100G, 200G, 400G, and 800G, including Auto-Negotiation and Link Training.
Experience verifying third-party mixed-signal IPs and integrating VIPs.
Strong interest in innovation across digital verification, including automation of repetitive activities and quality-improvement methods.
Proven experience working in a start-up-like environment.
Nice to have
Knowledge of DRAM controllers, DRAM PHYs, and HBM memory.
Culture & Benefits
Fast-paced early-stage startup environment.
Cross-functional collaboration with experts working from first principles.
Focus on innovation, industry trends, emerging technologies, and standards development.
Fun work environment with excellent benefits.
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