DV - Digital Verification Engineer (Senior levels - Staff +)

Location: On-site in Vancouver, BC, Canada, or the Bay Area, California, United States

Company

Early-stage chiplet startup developing high-performance connectivity technologies for chiplet-based systems.

What you will do

• Develop and execute verification plans for connectivity IPs and chiplets.
• Create, maintain, and debug SystemVerilog/UVM verification environments and block- and chip-level test cases.
• Maintain regression environments supporting design CI/CD pipelines, coverage analysis, and quality improvement.
• Collaborate with design engineers on microarchitecture, test-plan, coverage reviews, and progress toward RTL freeze.
• Verify Ethernet standards compliance, including 100G, 200G, 400G, and 800G clauses, Auto-Negotiation, and Link Training.
• Lead technical work for junior verification engineers and maintain DPI-based firmware simulation and GLS environments.

Requirements

• Master’s or Ph.D. in Electrical Engineering or a related field, with 6+ years of experience.
• Hands-on verification experience with serial transmission protocols and products, preferably retimers, gearboxes, or Ethernet PMA/PCS logic.
• Strong expertise in UVM, SystemVerilog test environments, and assertion coding.
• Experience with third-party regression-management and coverage-analysis tools, mixed-signal IP verification, and VIP integration.
• Experience with Ethernet IEEE 802.3 standards, including 100G–800G, Auto-Negotiation, and Link Training.
• Ability to work on-site in Vancouver, BC, or the Bay Area, CA.

Nice to have

• Knowledge of DRAM controllers/PHYs and HBM memory.
• Experience in a startup-like environment.

Culture & Benefits

• Fast-paced early-stage engineering environment focused on innovation and first-principles problem solving.
• Cross-functional collaboration with experts developing high-volume, high-performance manufacturable products.
• Excellent benefits and a fun work environment.