ASIC Verification Engineer (Semiconductors)

TL;DR

ASIC Verification Engineer (SystemVerilog/UVM): Developing and optimizing verification environments for high-speed interconnect physical layer transceivers (PHYs) with an accent on IEEE Ethernet protocols and chip architecture. Focus on building advanced testbench components, performing block and chip level verification, and creating infrastructure scripts for quality improvement.

Location: Onsite in Irvine, CA, USA

Salary: $101,000 – $162,000 per year

Company

Global leader and innovator in semiconductor solutions for wired and wireless communications.

What you will do

• Develop advanced verification environments and testbench components using SystemVerilog UVM.
• Execute block-level and chip-level verification tasks for communication ASICs.
• Analyze chip architecture, microarchitecture, and design specifications to ensure correctness.
• Implement verification for IEEE Ethernet protocols.
• Develop scripts and tools in Python, PERL, or TCL to improve verification efficiency and quality.

Requirements

• Educational background: Bachelor's in Engineering with 5+ years of experience, Master's with 3+ years, or a PhD.
• Must be proficient in HDL languages such as Verilog, SystemVerilog, or VHDL.
• Strong background in logic design and electronic circuit design.
• Must be based in the USA to work at the Irvine, CA office.

Nice to have

• Proficiency in C/C++ programming and Object-Oriented Programming (OOP).
• Experience with scripting languages including Python, PERL, or TCL.

Culture & Benefits

• Comprehensive medical, dental, and vision plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP) and competitive equity awards.
• Discretionary annual bonus.
• Paid sick leave, vacation time, and company holidays.