7 часов назад
Tech Lead Physical Design Engineer, Power Integrity
160 000 - 200 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Tech Lead Physical Design Engineer, Power Integrity (IR/EMIR): Driving power integrity analysis and closure for connectivity ASICs from early floorplan through tapeout with an accent on static and dynamic IR drop, electromigration, and multi-voltage power-aware sign-off. Focus on building scalable EMIR analysis flows, resolving power delivery and reliability issues, and converging complex SoC designs against foundry criteria.
Location: Fully on-site in San Jose, California, United States
Salary: $160,000–$200,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may be available.
Company
provides rack-scale AI infrastructure through connectivity solutions based on CXL, Ethernet, NVLink, PCIe, and UALink technologies, supported by the COSMOS software suite.
What you will do
- Own static and dynamic IR drop and electromigration analysis at block and full-chip levels through foundry sign-off.
- Drive UPF-based power-domain planning and power-aware sign-off for multi-voltage designs.
- Analyze thermal and current-density issues and recommend reliability improvements.
- Partner with package, power-grid, floorplan, implementation, RTL, STA, verification, IP vendor, and foundry teams to resolve voltage-drop hotspots and EM violations.
- Provide guidance on power-grid reinforcement, decap strategy, and hard-macro or SerDes integration.
- Develop EMIR runsets, stimulus methodologies, reporting dashboards, and automation infrastructure for efficient multi-corner analysis.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of experience in IR drop, electromigration analysis, and power-integrity sign-off for complex SoCs at 7nm and below.
- Deep expertise in power-grid design, PDN analysis, EM reliability mitigation, static and dynamic IR methodologies, and foundry sign-off criteria.
- Proficiency with Cadence Voltus and/or Synopsys RedHawk-SC or PrimeTime PX.
- Strong scripting ability in Tcl, Python, and/or Perl for flow automation and data analysis.
Nice to have
- Master's degree in Electrical Engineering or a related field.
- Power-integrity experience with high-speed SerDes, Ethernet PHY, or PCIe designs.
- Package-level power-delivery analysis or co-simulation, including advanced packaging or multi-die integration.
- Experience building EMIR methodology infrastructure across concurrent tapeout programs.
Culture & Benefits
- Bonus, incentives, and benefits may be available.
- Applications are encouraged from candidates with diverse backgrounds and experiences.
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