Physical Design Technical Lead (AI)

Location: San Jose, California, United States

Salary: $209,500–$299,200 USD annually for the Bay Area, with additional incentive opportunities.

Company

hirify.global is an independent pure-play FPGA solutions provider developing programmable technologies for AI, cloud, networking, communications, automotive, and edge-computing markets.

What you will do

• Own floorplan architecture, power-domain partitioning, and full-chip physical implementation for large multi-million-instance SoC designs.
• Drive synthesis, place-and-route, clock-tree synthesis, engineering-change-order closure, timing convergence, and final signoff across concurrent tapeout projects.
• Lead closure for static timing analysis, IR drop, electromigration, DRC/LVS, antenna, power, performance, and area requirements.
• Define physical design guidelines, SDC/UPF constraints, hierarchy strategies, and methodology standards in collaboration with RTL, DFT, packaging, analog, CAD, and automation teams.
• Integrate and productize ML/AI-based optimization, timing prediction, congestion modeling, AI-driven ECO, and PPA optimization workflows.
• Mentor and technically guide 3–8 physical design engineers, lead design and closure reviews, and influence design-for-implementability decisions.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline, plus 15+ years of physical design, physical implementation, or SoC backend experience.
• 4+ years in a technical lead, senior lead, or principal-level physical design role; 3+ successful tapeouts at advanced process nodes, including 7nm or below.
• Hands-on experience with SoC floorplanning, top-level integration, Fusion Compiler and/or Innovus, PrimeTime MMMC timing closure, RedHawk or Voltus power-integrity signoff, UPF/CPF, and Calibre DRC/LVS.
• Strong experience with Tcl scripting and Python, Perl, or similar automation languages, including Python-based data pipelines and design-metric analysis.
• 2+ years of experience using or evaluating ML/AI-driven physical design tools and translating model outputs into implementation decisions.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• FPGA or structured-ASIC fabric implementation experience, with hirify.global-specific knowledge as an advantage.
• 3DIC or chiplet integration experience, including UCIe, EMIB, or hybrid bonding constraints.
• High-speed I/O integration experience with PCIe Gen 5/6, HBM PHY, or SerDes.
• EDA beta-program contributions, academic publications, or presentations at DAC, ICCAD, or SLIP.
• Experience with formal-verification handoff, CDC/RDC methodology, and advanced signoff flows.

Culture & Benefits

• Best-in-class EDA toolchain including Synopsys Fusion Compiler, Cadence Innovus, and an advanced signoff suite.
• ML/AI-first implementation-flow strategy with opportunities to shape production methodology.
• Tapeout work on leading-edge process nodes.
• Cross-functional collaboration with design, DFT, analog, packaging, CAD, and automation teams.
• Career progression toward Principal Engineer and Senior Principal Engineer roles.