Physical Design - SOC Top Lead

Location: San Jose, CA; Pittsburgh, PA; or Austin, TX

Salary: $200,000–$250,000 per year, plus equity and comprehensive benefits.

Company

hirify.global develops energy-efficient general-purpose processors for continuous AI/ML and intelligent edge IoT applications.

What you will do

• Own top-level SoC physical design from block integration and floorplanning through timing, power, signal integrity, physical verification, and tapeout-ready GDS.
• Drive full-chip timing closure across all corners and modes, including cross-boundary timing and SDC ownership.
• Lead power planning, PDN design and analysis, IR-drop and EM closure, power-gating coordination, and chip-level noise analysis.
• Coordinate physical verification, clock and reset architecture, DFT integration, scan stitching, MBIST, JTAG, and ATPG coverage closure.
• Coordinate package/IO co-design, bump and ball maps, IO-ring planning, and package-aware floorplanning.
• Set chip-top implementation methodology, mentor block-level physical design engineers, and align DFT, DV, package, IO, and architecture teams on convergence and schedule risks.

Requirements

• Master’s degree in Electrical Engineering with 5+ years of industry experience, or a PhD in Electrical Engineering with 3+ years of industry experience.
• 8–12+ years of physical design experience and at least 2–3 full chip-top or SoC-integration tapeouts.
• Hands-on experience with advanced nodes and complex SoC timing closure across multiple corners and modes.
• Strong PDN, IR-drop, and EM analysis experience using Voltus or an equivalent tool, plus chip-level DFT integration experience.
• Fluency with Innovus or ICC2, Tempus or PrimeTime, RedHawk, and Calibre.
• Excellent scripting skills in TCL, shell, and Python, with the ability to lead technically across teams without direct reports.

Nice to have

• Package co-design experience with flip-chip or BGA, C4 bumps, and ball maps.
• Experience with non-standard architectures such as dataflow, tiled, or NoC-based designs.
• Experience integrating analog or mixed-signal macros at the top level.
• Knowledge of computer architecture, circuit design, device physics, and deep-submicron technology.

Culture & Benefits

• Opportunity to join a newly formed hardware engineering group during the early stages of product development.
• Significant ownership and influence over products progressing toward market release and scaled production.
• 401(k) matching and company-paid benefits.
• Equity program and paid parental leave.
• Flexibility and personal and professional development support.