Staff/ Principal Physical Design STA Engineer (AI Infrastructure)

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Execute STA flows and sign-off methodologies for high-performance semiconductor products used in demanding data center environments.
• Collaborate with Architecture, Design, DFT, and Backend teams on timing reviews and sign-off convergence.
• Develop, optimize, and manage SDC constraints across multi-scenario environments.
• Analyze cross-chip clock distribution networks and apply margining techniques across process corners.
• Improve design methodologies and automate sign-off workflows using industry-standard EDA tools and custom scripts.

Requirements

• B.Sc. in Electrical Engineering or Computer Engineering.
• 6+ years of hands-on STA experience at semiconductor companies, including work with advanced process technologies.
• Deep expertise in multi-scenario STA and timing constraint development and verification at block and subsystem levels.
• Strong understanding of OCV, AOCV, and POCV margining methodologies from synthesis through final sign-off.
• Solid knowledge of synthesis, place and route, physical verification, and their interaction with timing closure.

Nice to have

• Experience with Synopsys Timing Constraints Manager or Ausdia TimeVision.
• Experience executing STA on complex macro-level designs and supporting full-chip timing integration.
• Strong scripting skills in Tcl, Python, or Perl.

Culture & Benefits

• Opportunity to establish and take technical ownership within a new strategic R&D center in Israel.
• Work on chips addressing data bottlenecks in next-generation AI clusters.
• Inclusive environment welcoming diverse backgrounds and experiences.