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4 часа назад

Physical Design Expert (SoC)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Israel
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Physical Design Expert (SoC): Developing next-generation SoCs from RTL definition through GDS and tape-out with an accent on floorplanning, synthesis, place and route, timing analysis, and signoff verification. Focus on optimizing PPA, managing block and top-level constraints, and achieving full physical design convergence across advanced implementation flows.

Location: Haifa, Israel; on-site

Company

hirify.global develops technologies for accident prevention and semi- and fully autonomous vehicles.

What you will do

  • Own physical design blocks end to end, from RTL and initial constraints through GDS and full signoff.
  • Explore floorplans and collaborate with front-end design and architecture teams on RTL modifications and design reviews.
  • Perform synthesis activities including SDC definition, scan insertion, lint, LEC, UPF-LP, and SpyGlass verification.
  • Execute place and route from synthesis through final layout and signoff, targeting optimal PPA.
  • Manage block-level and top-level timing constraints and perform STA in collaboration with subsystem and full-chip owners.
  • Complete signoff across STA, IR/EM, physical verification, logic equivalence checking, and low-power verification.

Requirements

  • BSc or MSc degree in Computer Engineering or Electrical Engineering.
  • 8+ years of experience in physical design.
  • Experience with scripting languages such as Tcl, Python, Perl, or TCSH.
  • Strong communication skills, teamwork, customer orientation, and a can-do attitude.
  • Work on-site in Haifa, Israel.

Nice to have

  • Experience with high-speed interfaces such as DDR or PCIe.
  • Experience with advanced technology nodes, including 5nm and below.
  • Experience building or maintaining implementation tools and flows.

Culture & Benefits

  • Dynamic, startup-like R&D environment.
  • Deep technical ownership and high-level execution expectations.
  • End-to-end responsibility from initial definition through tape-out.
  • Close collaboration with design, architecture, subsystem, and full-chip teams.

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