Staff/Senior Staff Physical Design Floorplan & PDN Lead

Location: Bangalore, with 2 days of work required

Company

hirify.global develops advanced AI hardware and software systems for edge-to-cloud computing using high-efficiency in-memory computing technology.

What you will do

• Lead chip-level floorplanning, including macro placement, pin assignment, and partition definition for multi-million-gate designs.
• Architect and implement complex power delivery networks, defining metal stack usage and grid density.
• Perform static and dynamic IR-drop and electromigration analysis, diagnose root causes, and propose physical or architectural fixes.
• Collaborate with RTL and architecture teams on PPA trade-offs involving bus widths, pipeline stages, and memory configurations.
• Establish floorplanning and PDN synthesis methodologies and automated flows for the implementation team.

Requirements

• 10+ years of physical design experience and multiple successful tape-outs at 7nm, 5nm, or 3nm nodes.
• Expertise in complex PDN design, power-up sequence modeling, and multi-voltage domains.
• Deep proficiency in hierarchical physical design and top-level integration using Innovus or IC Compiler II.
• Strong understanding of thermal-aware PDN design and high-current-density paths.
• Advanced proficiency in Tcl, Python, or Perl for automation and data analysis.
• B.Tech/M.Tech in Electrical or Electronic Engineering, or equivalent.

Culture & Benefits

• Work within the RTL-to-GDSII / Physical Implementation department.
• Collaborate across RTL, architecture, and sign-off functions.
• Influence physical implementation practices used by the wider engineering team.