Senior Physical Design Engineer (AI Hardware)

Location: Bangalore, India — hybrid

Company

hirify.global develops advanced AI hardware and software systems for edge-to-cloud computing using in-memory computing technology for power-, energy-, and space-constrained applications.

What you will do

• Own physical implementation of complex blocks from synthesis and floor-planning through clock-tree synthesis, routing, and sign-off.
• Analyze timing paths, power profiles, and congestion to develop customized PPA optimization strategies.
• Use Tcl and Python to automate repetitive tasks, parse data, and improve the physical design environment.
• Converge partitions from RTL to clean GDSII while resolving DRC/LVS, ERC, IR drop, and timing violations.
• Collaborate with RTL and DFT teams to introduce physical constraints early and improve routing and timing outcomes.

Requirements

• 4–7 years of physical design experience, including 2–3 successful tape-outs.
• Hands-on experience with Cadence Innovus and Tempus.
• Proficiency in Tcl for tool control and Python for data parsing and flow automation.
• Experience improving power, performance, and area through floor-planning and placement tuning.
• Strong debugging skills in static timing analysis, EM/IR, and physical verification including DRC, LVS, and ERC.
• Ability to work independently, investigate root causes through logs and data, and challenge inefficient processes.

Culture & Benefits

• Work in an advanced silicon team focused on next-generation AI computing technology.
• Operate with a high degree of independence and ownership over complex partitions.
• Collaborate across physical design, RTL, and DFT disciplines.
• Apply a curiosity-driven, analytical approach to improving tools and design flows.