Senior / Staff Digital Verification Engineer (ASIC)

Location: On-site in Bristol, UK, or Austin, TX

Compensation: Bristol starting from £123K with equity; Austin starting from $217K with equity.

Company

hirify.global develops the DX-1 decode accelerator, a rack-scale AI hardware platform combining logic, data movement, packaging, optics, and interconnect.

What you will do

• Own end-to-end verification of high-throughput digital pipelines with continuous streaming data, deep pipelining, and robust handshaking.
• Build SystemVerilog/UVM verification environments with constrained-random testing, coverage closure, and regression automation.
• Implement assertion-based and formal verification for control logic, datapath correctness, CDC/RDC, protocol compliance, and equivalence checking.
• Model and validate algorithms with MATLAB/Simulink or Python, maintaining functional equivalence from algorithmic models through RTL and gate-level sign-off.
• Support FPGA prototyping and silicon bring-up through targeted test cases, debug strategies, and post-silicon validation.
• Collaborate with digital design, optical hardware, mixed-signal, and software teams while improving verification methodology, reuse, and documentation.

Requirements

• 5+ years of hands-on digital verification experience for high-performance ASICs or SoCs.
• Ownership of verification for a complex block or subsystem processing continuous real-time data streams.
• Strong SystemVerilog, SVA, and modern verification methodology experience, including UVM or CocoTB.
• Experience with GHz-class clock domains, CDC/RDC analysis, RTL simulation, formal verification, linting, STA, power intent, and gate-level simulation.
• Experience verifying high-speed interfaces such as SerDes, DDR/HBM, PCIe, or Ethernet.
• Proficiency with MATLAB/Simulink or Python/NumPy, plus solid knowledge of digital design, computer architecture, DSP, and semiconductor fundamentals.

Nice to have

• Tape-out experience on an advanced process node.
• Deep formal verification experience with property decomposition, coverage-driven formal, or Jasper.
• Exposure to coherent optical links, photonic-electronic co-design, AI/ML workloads, systolic arrays, tensor processors, arithmetic pipelines, or processor and ISA verification.
• Contributions to open-source RTL, verification frameworks, or FPGA platforms.

Culture & Benefits

• Meaningful equity and stock options.
• Annual living-local bonus for residences within 20 minutes of the office.
• Employer-contributed retirement plans.
• Eligibility to work is subject to U.S. export-control regulations and recent citizenship or permanent-residency status; applicants from certain restricted countries may be ineligible.