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Senior CPU Pre-Silicon Verification Engineer (SystemVerilog/UVM)

164 470 - 311 890$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR
Senior CPU Pre-Silicon Verification Engineer (SystemVerilog/UVM): Developing and executing functional verification for next-generation CPU logic, testbenches, and simulation models with an accent on microarchitecture coverage, performance, power, and timing analysis. Focus on debugging pre-silicon failures, improving scalable verification infrastructure, and collaborating with architecture, RTL, and physical design teams on complex CPU features.

Location: On-site in Austin, Texas, or Hillsboro, Oregon, United States

Salary: $164,470–$311,890 annual USD

Company

hirify.global develops semiconductor, CPU, and platform technologies for personal devices, data centers, and edge computing.

What you will do

  • Lead and execute functional verification of CPU logic against design specifications.
  • Develop IP verification plans, UVM-based testbenches, scalable verification environments, and coverage strategies.
  • Run system simulation models to analyze functionality, power, and timing and uncover design issues.
  • Replicate, debug, and identify root causes of failures in the pre-silicon environment.
  • Collaborate with CPU architects, RTL developers, and physical design teams on architectural and microarchitectural features.
  • Document verification plans, conduct technical reviews, improve verification methodologies, and lead a small team.

Requirements

  • Bachelor's degree in Electrical or Computer Engineering or a related field with 8+ years of relevant experience; or a master's degree with 7+ years; or a PhD with 4+ years.
  • Experience with design verification and validation methodologies, UVM, SystemVerilog, and industry-standard EDA tools.
  • Knowledge of digital logic design, including instruction set execution, ALUs, control units, registers, memory, and system buses.
  • Experience developing UVM-based testbenches for reusable and scalable verification environments.
  • Programming experience with C/C++ and SystemVerilog, plus at least one scripting language such as Python, Perl, or Bash.
  • Ability to work on-site in the United States.

Nice to have

  • RTL development experience and knowledge of x86 or other computer architectures.
  • Use of AI agents in verification.
  • Git experience and familiarity with Synopsys simulators.

Culture & Benefits

  • Work within hirify.global's Silicon and Platform Engineering Group on next-generation CPU and platform solutions.
  • Compensation includes competitive pay, stock bonuses, health benefits, retirement programs, and vacation.
  • Shift 1 schedule in the United States.

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