2 месяца назад
RTL Design Engineer (AI)
200 000 - 400 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
RTL Design Engineer (AI) (SystemVerilog/ASIC): Designing and verifying digital logic for thermodynamic hardware from microarchitecture through tapeout with an accent on synthesizable RTL, verification, and physical design collaboration. Focus on shaping novel computing architectures, closing coverage, meeting area and timing constraints, and supporting silicon bring-up.
Location: Hybrid in New York City, Silicon Valley, or London
Salary: $200,000–$400,000 annually, plus equity
Company
is an applied AI company developing foundational hardware and software for the semiconductor industry, AI infrastructure, and systems engineering.
What you will do
- Write and own synthesizable SystemVerilog RTL for datapath logic, control logic, and memory interfaces.
- Translate high-level specifications into implementable microarchitectures with the architecture team.
- Review verification plans, debug simulations and formal counterexamples, and help close coverage.
- Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
- Participate in design reviews and contribute to architecture decisions.
- Support tapeout preparation, integration, and post-silicon bring-up.
Requirements
- Production RTL development experience in SystemVerilog through synthesis and place-and-route.
- Experience closing coverage to a high level.
- At least one completed silicon tapeout.
- Experience with datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront.
- Strong debugging skills across simulation, waveforms, and formal verification.
- Industry experience in ASIC or SoC design and the ability to collaborate directly with architects and physical designers.
Nice to have
- Experience at an AI chip company with tightly coupled design and verification.
- Open-source RTL contributions to projects such as Chipyard, OpenTitan, or CVA6.
- Familiarity with RISC-V or other open instruction set architectures.
- Experience with AI-assisted RTL or EDA tools.
- Exposure to physical design constraints, floorplanning, or timing-driven RTL development.
Culture & Benefits
- Equitable compensation practices with salary reviewed based on role, skills, experience, and location.
- Equity included in the compensation package.
- Cross-functional collaboration across architecture, verification, physical design, and engineering teams.
- Inclusive workplace with equal employment opportunity and accessibility accommodations.
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