9 часов назад
Design Verification Engineer (AI)
200 000 - 400 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Design Verification Engineer (SystemVerilog/UVM/AI): Verify physics-inspired ASICs through testbench development, assertions, coverage closure, and tapeout support with an accent on AI-generated verification collateral and training-data quality. Focus on building end-to-end verification environments, evaluating EDA tooling, refining AI verification workflows, and supporting customer deployments.
Location: Hybrid in New York City, London, or Silicon Valley
Salary: $200,000–$400,000 base annually, plus equity
Company
is an applied AI company developing foundational hardware and software for the semiconductor industry, AI infrastructure, and advanced computing systems.
What you will do
- Own verification of internal physics-inspired ASICs, including testbench environments, assertions, functional coverage, and closure through tapeout.
- Review AI-generated verification collateral and collaborate with ML and product teams to improve product strategy and usability.
- Define verification training-data rubrics, curate golden examples, and set quality standards for model training.
- Support customer deployments by validating AI-generated collateral against customer specifications.
- Set up and evaluate EDA tools for internal and customer computing environments.
Requirements
- 5+ years of digital verification experience at a semiconductor or EDA tool company.
- Advanced SystemVerilog, UVM, and EDA verification-tool expertise, including vManager, Xcelium, and Jasper.
- Strong Python or Perl scripting skills.
- End-to-end verification experience covering test-plan creation, stimulus generation, and feature extraction.
- Excellent written and spoken communication skills.
- Willingness to support customer-facing deployments and occasional travel.
Nice to have
- Customer-facing, field-application, or forward-deployed engineering experience in semiconductors or EDA.
- Hands-on use of LLMs or agentic tools in verification workflows.
- Experience with analog, mixed-signal, or unconventional-compute verification.
Culture & Benefits
- Full-time hybrid work across New York City, London, and Silicon Valley.
- Equity included in the compensation package.
- Collaborative work across engineering, ML, product, data, and forward-deployed teams.
- Inclusive workplace with equal employment opportunity and accessibility accommodations.
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