Senior Mixed-Signal Verification Engineer (AI)

Location: On-site in Austin, Texas, United States. Eligibility is subject to U.S. export control regulations and recent citizenship or permanent residency status.

Salary: Starting from $264,000 annually in Austin, plus competitive compensation based on experience, skills, and location.

Company

Develops the hirify.global Decode Accelerator 1, a decode-focused AI computing solution using custom silicon, optics, and high-speed interconnect.

What you will do

• Own mixed-signal verification strategy and test plans from block level through subsystem and top-level integration.
• Define modeling fidelity across real-number models, Verilog-AMS, and transistor-level co-simulation, including model-versus-schematic equivalence checks.
• Build self-checking testbenches, reusable verification components, assertions, and functional coverage for CDRs, equalization, calibration loops, clocking, deserializers, and clock-domain crossings.
• Drive AMS co-simulation flows, regression infrastructure, and automation while improving simulation throughput.
• Debug analog/digital boundary failures, collaborate with analog and DSP designers, and translate specifications into models, tests, and interface contracts.
• Own verification sign-off through tape-out and contribute to silicon bring-up and measurement correlation.

Requirements

• BS or MS in Electrical Engineering or a related field and 5+ years of analog/mixed-signal verification experience on complex SoCs or mixed-signal IP.
• Hands-on experience with Verilog-AMS, real-number modeling, and analog-digital co-simulation using flows such as Spectre AMS or FastSpice coupled with a digital simulator.
• Strong SystemVerilog, assertion-based verification, self-checking testbench, reusable verification component, and UVM or constrained-random verification experience.
• Experience modeling analog blocks, validating models against transistor-level references, and debugging across the analog/digital boundary.
• Working knowledge of high-speed SerDes and wireline architectures, including CDRs, CTLE/DFE equalization, PLLs, samplers, slicers, serialization, and deserialization.
• Experience with calibration and adaptation loops, clock-domain crossings, scripting in Python/TCL/Make, mixed-signal IP tape-out sign-off, and silicon measurement correlation.

Culture & Benefits

• Meaningful stock options and ownership participation.
• Employer-contributed retirement plans.
• Annual Living-Local Bonus for employees residing within 20 minutes of the office.
• On-site work in Austin with compensation adjusted for experience, skills, and location.