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8 часов назад

Staff/Sr. Staff Design Verification (AI Photonics)

186 000 - 236 000$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Staff/Sr. Staff Design Verification (AI Photonics): Developing and executing verification methodologies, test plans, and scalable testbench components for integrated digital, analog, and photonic devices with an accent on UVM, AMS modeling, mixed-signal simulation, and emulation. Focus on closing coverage, validating block-level and full-chip designs, integrating analog IP, and verifying performance against system requirements.

Location: Boston, MA, United States; flexible hybrid workplace model

Salary: $186,000–$218,000 for Staff level; $206,000–$236,000 for Sr. Staff level. Base salary is supplemented by equity grants and performance-based rewards.

Company

hirify.global develops photonics-based infrastructure for AI and high-performance computing data centers, including its 3D-stacked Passage photonics engine.

What you will do

  • Define and enhance design verification methodologies for integrated digital, analog, and photonic devices, with emphasis on emulation.
  • Create and execute test plans for high-quality tapeouts meeting functional and performance goals.
  • Develop reusable, scalable UVM testbench components and verification environments for simulation and emulation.
  • Collaborate with architects, digital designers, DV engineers, and analog/photonics designers to define validation flows and understand system requirements.
  • Verify block-level and full-chip designs, close coverage, and complete DV signoff requirements using mixed-signal simulations.
  • Integrate analog IP and develop behavioral models, test cases, and checkers for upper-level verification.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience.
  • At least 8 years of design verification and SystemVerilog experience.
  • At least 2 years of Python experience.
  • Expertise developing with the UVM library.
  • Experience with Xcelium, ModelSim, Questa, or VCS simulators.
  • Strong problem-solving and collaboration skills; leveling depends on education, experience, and interview performance.

Nice to have

  • Master’s degree or higher in Electrical Engineering, Computer Engineering, a related field, or equivalent experience with 6 years of relevant experience.
  • Experience with post-silicon validation and debug.
  • Experience with AMS verification.

Culture & Benefits

  • Medical, dental, and vision coverage.
  • Retirement savings matching, life insurance, and disability coverage.
  • Vacation, sick leave, public holidays, and paid family leave.
  • Training and development support plus commuter benefits.
  • Equity grants for eligible full-time employees.

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