Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Очень мало
$120к-225к/год
$180к$210кмедиана$250к
По похожим ролям (50) ~ $210к/год
На СНГ рынке: $1.9к/мес ($1.8к - $3к)
65
Средняя вакансия
развернуть
Роль четко определена с ясным акцентом на верификацию дизайна для AI процессоров, но зарплата ниже рыночной средней, что может снизить ее привлекательность.
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Низкая зарплатаСтартап-средаЧеткие обязанностиСотрудничество в команде
Оценка от Hirify AI
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Senior Design Verification Engineer (AI Hardware): Developing and verifying digital dataflow architectures for next-generation AI processors with an accent on system-level and block-level verification, UVM testbenches, and coverage planning. Focus on verifying scheduling subsystems, interconnect fabrics, DMA engines, and memory controllers through simulation, modeling, emulation, and advanced verification strategies.
Location: Austin, TX or Palo Alto, CA; hybrid workplace.
Salary: $120,000–$225,000+ annually; actual compensation depends on experience, skills, qualifications, and location.
Company
hirify.global develops analog AI computing technology and AI processors for edge devices, cloud, and data center environments, including applications in drones, robotics, sensors, industrial systems, automotive, aerospace, and defense.
What you will do
Perform hands-on system-level and block-level verification of digital dataflow architectures for AI processors.
Develop test plans, coverage plans, verification infrastructure, and verification flows.
Develop and execute testbenches using UVM or other advanced design verification methodologies.
Use architecture models and emulation environments to verify large AI network functionality on the design.
Collaborate with RTL designers and architects to verify scheduling subsystems, interconnects, DMA engines, and memory controllers.
Work with architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure full-system correctness and reliability.
Requirements
Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
8+ years of industry experience developing verification testbenches.
Knowledge of verification methodologies such as UVM or similar.
Solid understanding of computer architecture, including datapaths, memory hierarchies, and interconnects.
Experience verifying one or more of the following: scheduling subsystems, high-performance interconnects, DMA engines, or memory subsystems.
Understanding of Verilog, SystemVerilog, and UVM.
Proven track record of first-pass silicon success.
Strong written and spoken communication skills.
Nice to have
Experience with emulation or FPGA prototyping for large-scale designs.
Knowledge of coverage-driven verification and advanced stimulus generation techniques.
Exposure to formal verification methods and tools.
Familiarity with power-aware and performance-driven verification flows.
Prior experience verifying AI, DSP, or other highly parallel architectures.
Strong scripting skills in Python or a similar language for automation and infrastructure development.
Culture & Benefits
Collaborative and respectful work environment.
Tools and support to enable high-quality engineering work.
Professionalism, creativity, integrity, and respect for diverse experiences and perspectives.
Focus on meaningful contribution and solving challenging problems together.
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