Design Engineer - Timing Methodology

Location: USA-California-San Jose-1320 Ridder Park Drive

Annual base salary: USD 143,800–230,000, plus discretionary annual bonus and equity awards.

Company

hirify.global develops advanced semiconductor and technology solutions, with this role supporting central engineering and chip design teams.

What you will do

• Develop and deploy timing sign-off methodologies for advanced technology nodes.
• Design and implement sign-off solutions for SOC, 3D/2.5D IC, and multi-die designs.
• Participate in and lead EDA flow development using Primetime, Tempus, and Innovus.
• Conduct complex studies, statistical data analysis, and modeling to improve timing, yield, and design margins.
• Collaborate with engineering experts and internal and external partners in a project-oriented agile environment.
• Own multiple project responsibilities and drive practical, high-quality solutions to completion.

Requirements

• BS degree in EE/CS with 12+ years of industry experience, or MS/Ph.D. degree in EE/CS with 10+ years of industry experience.
• Strong hands-on experience developing and owning timing sign-off methodologies for SOC and 3D/2.5D IC designs.
• Experience with advanced silicon technologies, production testability, yield, and tapeout of complex high-volume SOCs.
• Strong experience with industry-standard STA tools, including Primetime and Tempus.
• Programming and flow-automation experience with TCL, Python, Perl, and Unix shell.
• Strong analytical, communication, multitasking, problem-solving, and autonomous execution skills.

Culture & Benefits

• Fast-paced, project-oriented agile working environment.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Employee Assistance Program, paid holidays, paid sick leave, and vacation time.
• Paid family leave and other legally applicable leaves of absence.
• Equal opportunity employment and consideration under applicable federal, state, and local laws.