Design Automation Engineer (FPGA/EDA)

Location: San Jose, California, United States

Salary: $95,000–$110,000 USD per year for the Bay Area, California.

Company

hirify.global develops programmable solutions including FPGAs, SoCs, CPLDs, IP, development tools, SmartNICs, and IPUs for applications ranging from cloud to edge computing.

What you will do

• Develop, maintain, and support static timing analysis flows.
• Improve timing models, methodologies, flow robustness, and timing closure.
• Collaborate with CAD, design, and design automation teams on flow integration.
• Design, develop, test, and debug software tools, flows, and methodologies for hardware design and manufacturing.
• Capture user stories and requirements and write functional and test code.
• Automate build and deployment and perform unit, integration, and end-to-end testing.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 1 year of experience in static timing analysis, Liberty model format, and methodology or flow development.
• At least 1 year of scripting experience with Python, Perl, Tcl, or Shell.
• Hands-on experience with Synopsys PrimeTime and Cadence Tempus.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Experience with Liberty model characterization and STA-tool-based Liberty model extraction.
• Familiarity with Fusion Compiler, Innovus, Cadence Pegasus, and other EDA tools.
• Strong understanding of digital circuit design and simulation.

Culture & Benefits

• Regular full-time employment.
• Incentive opportunities based on individual and company performance.
• Work is aligned with Shift 1 in the United States of America.