Senior Staff Engineer (ASIC Design)

TL;DR

Senior Staff Engineer (ASIC Design): Developing and validating timing constraints for complex SoC designs with an accent on STA signoff methodologies and timing closure. Focus on optimizing high-speed designs in advanced technology nodes (5nm/4nm) and collaborating across architecture and RTL teams to ensure performance, power, and area goals.

Location: Must be based in Irvine, CA

Salary: $135,900–$201,130 per annum

Company

hirify.global is a leading semiconductor company providing essential data infrastructure solutions for enterprise, cloud, and AI architectures.

What you will do

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to define timing modes and constraints.
• Perform static timing analysis (STA) using industry-standard tools like Primetime.
• Define and implement timing signoff methodologies, including process corners and derates.
• Automate STA processes and flows using Tcl or Python.
• Conduct post-route timing checks and quality of results (QoR) analysis.

Requirements

• Must be eligible to access export-controlled information under U.S. law.
• Bachelor’s or Master’s degree in Computer Science or Electrical Engineering.
• Minimum 5 years of industry experience in ASIC timing and STA.
• Strong understanding of ASIC design flows from RTL to GDSII.
• Proficiency in STA tools and scripting languages (Tcl, Perl, Python).
• Experience with high-complexity silicon in advanced technology nodes (e.g., TSMC N4/N5).

Culture & Benefits

• Comprehensive benefits including financial well-being, family support, and mental health resources.
• Employee stock purchase plan with a 2-year look back.
• Recognition and service awards program.
• Commitment to professional growth and leadership development.