Timing Engineer (FPGA)

Location: San Jose, California, United States; onsite role

Salary: $118,900–$172,000 USD annually for the Bay Area, California.

Company

hirify.global is a pure-play FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Drive timing closure at block and subsystem levels through implementation and final sign-off.
• Develop timing methodologies, flows, and scripts for hierarchical and full-chip interface timing closure.
• Define and manage I/O timing budgets across hierarchical designs.
• Perform advanced sign-off analysis using POCV, OCV, PVT effects, and multi-corner/multi-mode runs.
• Provide root-cause analysis, actionable timing feedback, and ECO guidance to RTL, physical design, and full-chip teams.
• Plan global clocks and optimize timing convergence across multidisciplinary engineering teams.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 5+ years of experience in ASIC or FPGA timing analysis, static timing analysis, and timing sign-off.
• 5+ years of experience with timing constraints, timing closure, synthesis, place-and-route, and parasitic extraction flows.
• Experience applying OCV, POCV, and PVT analysis to leading-edge semiconductor technologies at 5nm or below.
• Experience with Cadence Tempus, Synopsys PrimeTime, and multi-corner/multi-mode timing analysis.
• Experience developing automation and scripting solutions with Tcl, Python, and/or Perl, plus strong cross-functional collaboration skills.

Nice to have

• Experience with advanced FPGA or high-performance ASIC designs.
• Experience developing timing methodologies and automation for large-scale hierarchical designs.
• Experience defining hierarchical timing budgets, validating timing ECOs, and driving interface timing closure.
• Familiarity with clock tree synthesis, clock planning, and clock architecture optimization.

Culture & Benefits

• Regular full-time employment with incentive opportunities based on individual and company performance.
• Collaboration across Design, Architecture, Physical Design, RTL, implementation, and full-chip teams.
• Artificial intelligence may be used to screen, assess, or select applicants.
• Applicants must be eligible for any required U.S. export authorizations.