Manager, Static Timing Analysis (STA) (FPGA)

Location: Toronto, Ontario, Canada

Estimated salary range: CAD 144.6K–209.3K annually, plus performance-based incentive opportunities.

Company

hirify.global develops next-generation FPGA platforms for AI, data center, and networking applications.

What you will do

• Build, manage, and mentor a high-performing static timing analysis team.
• Own end-to-end timing closure and signoff for advanced FPGA designs, including constraint development and timing analysis.
• Define and implement STA methodologies, flows, and best practices to improve timing convergence and design quality.
• Collaborate with RTL design, synthesis, physical design, place-and-route, and architecture teams to resolve timing issues.
• Drive performance, power, and area improvements through timing-driven design and optimization.
• Deliver timing closure milestones on schedule across multiple programs and use industry-standard EDA tools to debug violations and automate flows.

Requirements

• 10+ years of experience in static timing analysis for ASIC or FPGA designs.
• 3+ years of experience managing or leading engineering teams.
• Deep knowledge of setup and hold analysis, clock domain crossing, timing constraints, and timing closure methodologies.
• Strong experience with timing signoff tools such as PrimeTime or equivalent, plus synthesis, place-and-route, and full-chip implementation flows.
• Experience with RTL design using Verilog or SystemVerilog and analysis of low-power and high-performance design challenges.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Applicants must be eligible for any required Canada export authorizations.

Nice to have

• Experience with FPGA architecture and design flows, advanced nodes, and high-speed designs.
• Scripting and automation experience with Tcl or Python for timing analysis.
• Experience working in large-scale, distributed engineering environments.

Culture & Benefits

• Work on critical STA efforts for next-generation FPGA platforms.
• Collaborate with engineering teams across silicon design and implementation.
• Performance-based incentive opportunities recognize individual and company-wide contributions.
• Canadian work experience is not required.