Physical Design Engineering, VP (AI)
ΠΡΡΡ & Π‘ΠΎΠΏΡΠΎΠ²ΠΎΠ΄
ΠΠ»Ρ ΠΌΡΡΡΠ° Ρ ΡΡΠΎΠΉ Π²Π°ΠΊΠ°Π½ΡΠΈΠ΅ΠΉ Π½ΡΠΆΠ΅Π½ Plus
ΠΠΏΠΈΡΠ°Π½ΠΈΠ΅ Π²Π°ΠΊΠ°Π½ΡΠΈΠΈ
Location: San Jose, California, United States
Salary: $250,600β$375,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may also apply.
Company
provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.
What you will do
- Lead end-to-end physical design execution for complex multi-die switching products using UCIe and UALink.
- Drive chip-level floorplanning, power planning, placement, routing, timing closure, and signoff for advanced-node designs.
- Establish methodologies for interposer-based chiplet architectures and die-to-die interfaces.
- Build, scale, and mentor a physical design organization, including Directors, Managers, and senior engineers.
- Partner with architecture, digital design, packaging, silicon engineering, DFT, HR, and recruiting teams.
- Resolve timing, power, signal integrity, and manufacturability challenges in high-speed SerDes and switching fabrics.
Requirements
- Bachelorβs degree in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years of experience in physical design and implementation of complex SoCs or ASICs.
- Successful delivery of multiple tapeouts in advanced process nodes, including 7nm or below.
- Deep expertise in chiplet architectures, interposer design, die-to-die interface implementation, and 2.5D/3D integration.
- Expert knowledge of physical design flows, timing closure, power optimization, and signoff methodologies.
- Experience managing and scaling engineering teams of 20+ people.
Nice to have
- Masterβs degree or PhD in Electrical Engineering or a related field.
- Experience with UCIe, PCIe Gen 6/7, or other high-speed SerDes physical implementation.
- Background in AI/ML infrastructure, networking ASICs, or high-performance switching products.
- Expertise with Cadence and/or Synopsys physical design tools and flows.
- Experience with advanced DFT integration, DFM, and physical design automation.
Culture & Benefits
- Focus on technical excellence, innovation, and collaboration.
- Opportunity to work on connectivity technologies for hyperscale AI data centers.
- Bonus, incentives, and benefits may be available.
- Commitment to an inclusive workplace that welcomes diverse backgrounds and experiences.
ΠΡΠ΄ΡΡΠ΅ ΠΎΡΡΠΎΡΠΎΠΆΠ½Ρ: Π΅ΡΠ»ΠΈ ΡΠ°Π±ΠΎΡΠΎΠ΄Π°ΡΠ΅Π»Ρ ΠΏΡΠΎΡΠΈΡ Π²ΠΎΠΉΡΠΈ Π² ΠΈΡ ΡΠΈΡΡΠ΅ΠΌΡ, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡ iCloud/Google, ΠΏΡΠΈΡΠ»Π°ΡΡ ΠΊΠΎΠ΄/ΠΏΠ°ΡΠΎΠ»Ρ, Π·Π°ΠΏΡΡΡΠΈΡΡ ΠΊΠΎΠ΄/ΠΠ, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡΠ΅ ΡΡΠΎΠ³ΠΎ - ΡΡΠΎ ΠΌΠΎΡΠ΅Π½Π½ΠΈΠΊΠΈ. ΠΠ±ΡΠ·Π°ΡΠ΅Π»ΡΠ½ΠΎ ΠΆΠΌΠΈΡΠ΅ "ΠΠΎΠΆΠ°Π»ΠΎΠ²Π°ΡΡΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡΠΈΡΠ΅ Π² ΠΏΠΎΠ΄Π΄Π΅ΡΠΆΠΊΡ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β