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17 часов Π½Π°Π·Π°Π΄

Physical Design Engineering, VP (AI)

250Β 600 - 375Β 000$
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
c_level
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

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TL;DR
Physical Design Engineering, VP (AI): Leading full-chip physical design for complex multi-die switching products with UCIe and UALink connectivity, with an accent on chiplet architectures, advanced packaging, and high-performance implementation. Focus on scaling physical design teams, establishing methodologies, closing timing and power targets, and delivering multiple advanced-node tapeouts.

Location: San Jose, California, United States

Salary: $250,600–$375,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may also apply.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

  • Lead end-to-end physical design execution for complex multi-die switching products using UCIe and UALink.
  • Drive chip-level floorplanning, power planning, placement, routing, timing closure, and signoff for advanced-node designs.
  • Establish methodologies for interposer-based chiplet architectures and die-to-die interfaces.
  • Build, scale, and mentor a physical design organization, including Directors, Managers, and senior engineers.
  • Partner with architecture, digital design, packaging, silicon engineering, DFT, HR, and recruiting teams.
  • Resolve timing, power, signal integrity, and manufacturability challenges in high-speed SerDes and switching fabrics.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 15+ years of experience in physical design and implementation of complex SoCs or ASICs.
  • Successful delivery of multiple tapeouts in advanced process nodes, including 7nm or below.
  • Deep expertise in chiplet architectures, interposer design, die-to-die interface implementation, and 2.5D/3D integration.
  • Expert knowledge of physical design flows, timing closure, power optimization, and signoff methodologies.
  • Experience managing and scaling engineering teams of 20+ people.

Nice to have

  • Master’s degree or PhD in Electrical Engineering or a related field.
  • Experience with UCIe, PCIe Gen 6/7, or other high-speed SerDes physical implementation.
  • Background in AI/ML infrastructure, networking ASICs, or high-performance switching products.
  • Expertise with Cadence and/or Synopsys physical design tools and flows.
  • Experience with advanced DFT integration, DFM, and physical design automation.

Culture & Benefits

  • Focus on technical excellence, innovation, and collaboration.
  • Opportunity to work on connectivity technologies for hyperscale AI data centers.
  • Bonus, incentives, and benefits may be available.
  • Commitment to an inclusive workplace that welcomes diverse backgrounds and experiences.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’