18 часов назад
Manager, Physical Design Engineer
180 000 - 220 000CAD
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Manager, Physical Design Engineer (ASIC/SoC): Leading physical design execution for high-speed connectivity ASICs from RTL to GDSII with an accent on floorplanning, place-and-route, timing closure, and sign-off at advanced process nodes. Focus on building and mentoring the Toronto physical design team, integrating SerDes and hard macros, and driving convergence across multiple tapeouts.
Location: Fully onsite in Toronto, Ontario, Canada
Salary: CAD 180,000–220,000 base salary per year, depending on experience, level, and business need. The role may also include discretionary bonuses, incentives, and benefits.
Company
provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for hyperscalers and large data centers.
What you will do
- Lead and mentor the Toronto physical design engineering team and own team development.
- Drive block- and top-level physical design implementation for retimer and signal-conditioning ASICs from floorplanning through tapeout.
- Own the physical design flow from RTL to GDSII, including synthesis, place-and-route, clock-tree synthesis, extraction, timing closure, and sign-off.
- Collaborate with RTL, DFT, STA, EMIR, verification, and IP vendor teams to achieve design convergence.
- Coordinate with physical design teams in San Jose, Irvine, and Bangalore on methodology and design quality.
- Establish best practices, flow improvements, quality checks, hiring processes, career development, and sprint planning for concurrent programs.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field; a Master’s degree is preferred.
- 10+ years of experience implementing complex SoCs at advanced nodes, including 7nm and below.
- 2+ years of experience leading teams or projects, with demonstrated mentoring and engineer development experience.
- Hands-on experience with synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
- Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler or ICC2, plus strong scripting skills in Tcl, Python, and/or Perl.
- Ability to work fully onsite at the Toronto location.
Nice to have
- Deep knowledge of high-speed SerDes physical layers, including equalization, CDR, and signal integrity.
- Understanding of physical-layer timing challenges in high-speed serial interfaces.
- Experience building and scaling physical design teams through multiple tapeouts.
- Knowledge of agentic AI solutions for EDA automation.
Culture & Benefits
- Opportunity to work on connectivity products deployed in large AI clusters and hyperscale data centers.
- Collaboration with global physical design teams and ecosystem partners.
- Discretionary bonus, incentives, and benefits may be available.
- encourages applications from people with diverse backgrounds and experiences.
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