Senior/Staff Physical Design Engineer (AI Semiconductor)

Location: Haifa District, Israel

Company

hirify.global develops rack-scale AI infrastructure through semiconductor connectivity solutions based on CXL, Ethernet, NVLink, PCIe, and UALink technologies, supported by its COSMOS software suite.

What you will do

• Join the founding backend engineering team and help establish local physical design standards and execution methodologies.
• Own the RTL-to-GDS physical implementation flow, including synthesis, floorplanning, place and route, and clock-tree synthesis.
• Lead macro-level implementation, complex routing, and physical design execution for advanced semiconductor chips.
• Drive signoff activities including static timing analysis, physical verification, reliability analysis, and logic equivalence checking.
• Collaborate with architecture, design, and DFT teams on advanced process nodes and high-speed connectivity.
• Develop TCL or Python automation to improve EDA workflows and engineering productivity.

Requirements

• Bachelor’s degree in Electrical Engineering or a related technical field.
• 3+ years of hands-on physical design experience at semiconductor companies.
• Deep experience with the complete RTL-to-GDS flow, including macro implementation, floorplanning, and complex routing.
• Experience with advanced process technologies at 7nm and below.
• Experience with STA, LEC, DRC, and EMIR signoff tools and flows.
• Proficiency in TCL or Python scripting for EDA tool automation.

Nice to have

• Full-chip implementation and integration experience.
• Knowledge of power, signal integrity, and power integrity analysis.
• Familiarity with DFT requirements and their impact on physical layout.
• Experience with Synopsys Fusion Compiler, ICC2, or Cadence Innovus.
• Background in high-speed interface designs or connectivity protocols.

Culture & Benefits

• Opportunity to help build a new strategic R&D center and local backend engineering organization.
• Meaningful ownership of physical implementation and backend methodology for AI infrastructure chips.
• Inclusive environment that encourages applications from people with diverse backgrounds and experiences.