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9 часов назад

Senior Engineer - Design (ASIC/SoC)

86 000 - 186 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Senior Engineer - Design (ASIC/SoC): Developing next-generation storage controller devices and owning complex digital subsystems from architecture and RTL design through verification, silicon bring-up, and post-silicon support with an accent on SystemVerilog/VHDL, AXI/AMBA integration, CDC, and low-power design. Focus on implementing SAS/SATA protocol logic, closing verification, debugging silicon issues, and mentoring engineers while coordinating cross-functional delivery of production-quality silicon.

Location: Burnaby, Canada

Annual base salary: $86,000–$186,000, plus restricted stock units and quarterly bonuses.

Company

hirify.global develops semiconductor products and solutions, including advanced storage controller devices for datacenter applications.

What you will do

  • Own the architecture, micro-architecture, and synthesizable RTL implementation of complex digital subsystems ranging from 100K to 10M+ gates.
  • Design and integrate RTL using SystemVerilog, Verilog, and VHDL, including AXI/AMBA interconnects, bus fabrics, bridges, and compliant interfaces.
  • Implement CDC schemes and low-power techniques such as clock gating, power gating, and multi-voltage UPF flows.
  • Develop verification plans and drive closure using SystemVerilog, UVM, formal verification, simulation, emulation, and validation methods.
  • Implement SAS and SATA protocol logic and resolve complex design, integration, and hardware issues with cross-functional teams.
  • Lead post-silicon bring-up, characterization, lab debug, design reviews, and mentoring of junior engineers.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or an equivalent field.
  • Typically 7+ years of professional experience in digital ASIC/SoC design and verification.
  • Strong RTL design and verification expertise with SystemVerilog, VHDL, UVM, and/or formal verification.
  • Hands-on experience with AXI/AMBA, CDC design and analysis, low-power methodologies, and UPF/CPF multi-voltage flows.
  • Working knowledge of SAS and SATA protocols, post-silicon bring-up, validation, lab debug, and industry verification tools.
  • Excellent verbal and written English communication skills, plus scripting and programming experience with tools such as Python, Perl, Tcl, or Make.

Nice to have

  • Hardware emulation and FPGA prototyping experience.
  • Experience with DFT and timing closure.
  • Familiarity with NVMe, PCIe, or other storage and high-speed interface protocols.
  • Experience defining and improving design and verification methodologies across a team.

Culture & Benefits

  • Health benefits beginning on the first day.
  • Retirement savings plans and an employee stock purchase program with a six-month look-back feature.
  • Restricted stock units and quarterly bonus payments as part of the compensation package.
  • Leadership and employee development programs.
  • Travel requirement of 0%–25%.

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