Senior Principal Digital Design Engineer (AI Infrastructure)

Location: San Jose, CA, United States

Salary: $205,000–$255,000 per year, depending on experience, level, and business need. The role may also include discretionary bonus, incentives, and benefits.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and a software suite integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Define micro-architectures for complex digital blocks and subsystems across multiple product lines.
• Lead RTL implementation from architecture definition through GDS and silicon bring-up.
• Drive performance, power, and area trade-offs, timing constraints, closure strategies, and DFT methodologies.
• Partner with verification, physical design, DFT, post-silicon, firmware, and software teams on integration, testing, debugging, and hardware-software interfaces.
• Mentor engineers and improve silicon development processes, CAD automation, and design infrastructure.
• Influence product roadmaps, technical standards, design reviews, and production delivery.

Requirements

• Bachelor’s degree in Electrical Engineering or equivalent.
• 12+ years of hands-on experience developing complex SoC or silicon products in server, storage, and/or networking markets.
• Expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure.
• Deep knowledge of at least one high-speed protocol, such as PCIe, CXL, Ethernet, or DDR.
• Production experience with advanced CMOS nodes of 7 nm or smaller.
• Proficiency with Cadence and/or Synopsys digital design flows, with a record of delivering multiple high-performance designs to production.

Nice to have

• Master’s degree in Electrical Engineering or a related field.
• Experience with multiple high-speed protocols, including PCIe Gen 5/6, CXL, UALink, Ethernet, and DDR4/DDR5.
• Experience collaborating with embedded firmware teams and familiarity with RISC-V or Arm subsystems.
• Contributions to design methodology, CAD automation, or infrastructure improvements.
• Experience leading technical teams or cross-functional initiatives in data center environments.

Culture & Benefits

• Discretionary bonus, incentives, and benefits may be available.
• Work is supported by collaboration across verification, physical design, DFT, post-silicon, firmware, and software functions.
• Inclusive environment encouraging applications from people with diverse backgrounds and experiences.