Senior Principal Engineer, Micro-architecture and RTL (Embedded)

Location: Santa Clara, CA. Applicants must be eligible to access export-controlled information as defined under U.S. law.

Salary: $182,360 – $273,200 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Design, develop, and implement micro-architecture and RTL for complex power management ICs.
• Collaborate with system and chip architects to create industrial-quality implementations.
• Manage the full design development cycle, from writing micro-architecture docs to silicon bring-up and IP maintenance.
• Produce comprehensive block micro-architecture and register specifications.
• Supervise and mentor other digital design engineers.
• Evaluate and improve design and verification methodologies.

Requirements

• Bachelor's degree in CS or EE (15+ years experience), Master's (10-12 years), or PhD (8-10 years).
• Expertise in System Verilog RTL coding and System Verilog Assertions.
• Experience with Universal Verification Methodology (UVM).
• Proven success in project leadership and creating modular/reusable design components.
• Strong knowledge of embedded micro-controller systems.
• Eligibility to access technology subject to U.S. export control laws (EAR).

Nice to have

• Experience with Ethernet, PCIe, and CXL.
• Knowledge of power conversion systems.

Culture & Benefits

• Comprehensive financial well-being programs, including an employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards for professional contributions and milestones.