FPGA/RTL Engineer (Optical Communications)

Location: On-site in San Carlos, California, United States

Salary: $150,000–$200,000 annually

Company

hirify.global is building satellite infrastructure for the orbital economy, including space-based energy generation, optical communications, and on-orbit computing.

What you will do

• Design, implement, and verify SystemVerilog/Verilog HDL for FPGA subsystems across architecture, synthesis, timing closure, and on-orbit operation.
• Build FPGA logic for free-space optical communication links, including modem interfaces, framing, synchronization, and high-throughput data pipelines.
• Develop 10/25/40/100GbE MAC/PCS logic, SERDES/transceiver configurations, DDR/DMA datapaths, and link-layer framing.
• Define AXI memory-mapped interfaces and hardware/software contracts with flight-software engineers.
• Create simulation and testbench environments, validate hardware with laboratory instruments, and lead board bring-up and payload avionics integration.
• Investigate optical-link, ground, and software-chain anomalies, drive root-cause fixes, and document FPGA designs and interfaces.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of FPGA/HDL design experience, including architecture, verification, synthesis, and timing closure.
• Production experience with SystemVerilog or Verilog and Xilinx/AMD FPGA platforms, including Zynq UltraScale+, Vivado, and Vitis.
• Experience with high-speed digital interfaces, DDR/DMA-based datapaths, multi-gigabit data pipelines, and embedded-software integration.
• Hands-on hardware bring-up and laboratory debugging with oscilloscopes, logic analyzers, and embedded debug tools.
• Must meet U.S. ITAR eligibility requirements, including U.S. citizenship, lawful permanent residency, protected-individual status, or eligibility to obtain required authorizations.

Nice to have

• Experience in aerospace, defense, semiconductor, or other high-reliability development.
• Experience with free-space or fiber optical communications, optical modems, high-speed transceivers, or Ethernet protocol layers in FPGA fabric.
• Familiarity with Versal ACAP, Quartus, Questa/ModelSim, Xcelium, Verilator, UVM, C/C++, Python, and TCL.
• Experience with hardware-in-the-loop testing, automated regression, fault-tolerant design, and radiation-effects mitigation.

Culture & Benefits

• Small, fast-moving team with high ownership from the first day.
• Opportunity to work on a live flight program with near-term launch milestones and see designs operate in orbit.
• Equity in hirify.global, medical, dental, and vision insurance, and a 401(k) retirement savings plan.
• Paid time off, 10 paid holidays, and paid parental leave.
• Relocation assistance if applicable, daily office lunch, and a stocked kitchen.